Yu-hsin Wang 360b7b06a4 dev-arm: Fix VExpressFastmodel interrupt configs ...

HDLcd interrupt params should receive ArmSPI class

Change-Id: I4a5dacdfe5803511d19f2ed789017fb3b1857bdb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36455
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2020-10-23 04:31:48 +00:00

..

arch

x86: Move syscall handling for Linux into the EmuLinux workload.

2020-10-22 22:03:55 +00:00

base

base,sim: Move BitUnion serialization support to bitunion.hh.

2020-10-22 22:02:26 +00:00

cpu

cpu: Remove unused demapInstPage and demapDataPage

2020-10-21 09:33:39 +00:00

dev

dev-arm: Fix VExpressFastmodel interrupt configs

2020-10-23 04:31:48 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

misc: Use compiler.hh macros when available.

2020-10-19 05:52:40 +00:00

kern

misc: Update attribute syntax, and reorganize compiler.hh.

2020-09-28 21:52:59 +00:00

learning_gem5

misc: Standardize the way create() constructs SimObjects.

2020-10-14 12:06:44 +00:00

mem

mem-ruby: L1/L2 hit/miss tracking for MOESI_AMD_BASE/GPU_VIPER

2020-10-22 14:47:06 +00:00

proto

misc: Use the protobuf version to choose between ByteSize(Long).

2020-04-29 21:46:11 +00:00

python

sim,python: Flip logic on loopback listeners

2020-10-16 15:09:52 +00:00

sim

base,sim: Move BitUnion serialization support to bitunion.hh.

2020-10-22 22:02:26 +00:00

systemc

misc: Standardize the way create() constructs SimObjects.

2020-10-14 12:06:44 +00:00

unittest

base: Make the Value stat's functor method accept lambdas.

2020-09-01 21:57:34 +00:00

Doxyfile

misc: Changed gem5 version info for gem5 20.2 dev

2020-10-01 17:37:53 +00:00

SConscript

scons: Simplify arch enum generation

2020-09-07 08:42:07 +00:00