gem5/src/cpu at 34ad1123ee5927e3b1503f07649620a533d3eab9 - gem5

checker

arch: Make readMiscRegNoEffect const throughout

2015-02-16 03:33:28 -05:00

inorder

cpu: re-organizes the branch predictor structure.

2015-04-13 17:33:57 -05:00

kvm

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

minor

cpu: re-organizes the branch predictor structure.

2015-04-13 17:33:57 -05:00

nocpu

arch, cpu: Factor out the ExecContext into a proper base class

2014-09-03 07:42:22 -04:00

o3

cpu: re-organizes the branch predictor structure.

2015-04-13 17:33:57 -05:00

pred

cpu: re-organizes the branch predictor structure.

2015-04-13 17:33:57 -05:00

simple

cpu: re-organizes the branch predictor structure.

2015-04-13 17:33:57 -05:00

testers

cpu: Fix TrafficGen message format

2015-03-19 04:06:12 -04:00

activity.cc

Fix: Address a few benign memory leaks

2012-07-09 12:35:30 -04:00

activity.hh

cpu: Useful getters for ActivityRecorder

2014-05-09 18:58:48 -04:00

base_dyn_inst_impl.hh

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

base_dyn_inst.hh

cpu: o3 register renaming request handling improved

2015-03-02 04:00:38 -05:00

base.cc

cpu: fix RetiredStores probe point

2015-01-10 14:30:53 -06:00

base.hh

cpu: remove legion tracer

2015-01-25 07:22:05 -05:00

BaseCPU.py

mem: Move crossbar default latencies to subclasses

2015-03-02 04:00:47 -05:00

CheckerCPU.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

cpuevent.cc

…

cpuevent.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

CPUTracers.py

cpu: Put all CPU instruction tracers in a single file

2015-01-25 07:22:17 -05:00

decode_cache.hh

ISA,CPU: Generalize and split out the components of the decode cache.

2012-05-26 13:45:12 -07:00

dummy_checker.cc

sim: Add the notion of clock domains to all ClockedObjects

2013-06-27 05:49:49 -04:00

dummy_checker.hh

cpu: Add header files for checker CPUs

2012-11-02 11:32:01 -05:00

DummyChecker.py

cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy

2013-02-15 17:40:08 -05:00

exec_context.cc

arch, cpu: Factor out the ExecContext into a proper base class

2014-09-03 07:42:22 -04:00

exec_context.hh

x86 isa: This patch attempts an implementation at mwait.

2014-11-06 05:42:22 -06:00

exetrace.cc

sim: Clean up InstRecord

2015-01-25 07:22:44 -05:00

exetrace.hh

cpu: Remove all notion that we know when the cpu is misspeculating.

2015-01-25 07:22:26 -05:00

func_unit.cc

…

func_unit.hh

Param: Transition to Cycles for relevant parameters

2012-09-07 12:34:38 -04:00

FuncUnit.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

inst_pb_trace.cc

cpu: add support for outputing a protobuf formatted CPU trace

2015-02-16 03:32:38 -05:00

inst_pb_trace.hh

cpu: Fix InstPBTrace inheritance

2015-03-26 11:16:43 -04:00

inst_seq.hh

build: fix compile problems pointed out by gcc 4.4

2009-11-04 16:57:01 -08:00

InstPBTrace.py

cpu: add support for outputing a protobuf formatted CPU trace

2015-02-16 03:32:38 -05:00

inteltrace.cc

gcc: Clean-up of non-C++0x compliant code, first steps

2012-03-19 06:36:09 -04:00

inteltrace.hh

cpu: Remove all notion that we know when the cpu is misspeculating.

2015-01-25 07:22:26 -05:00

intr_control_noisa.cc

arch: Resurrect the NOISA build target and rename it NULL

2013-09-04 13:22:57 -04:00

intr_control.cc

SE/FS: Get rid of FULL_SYSTEM in the CPU directory.

2011-11-18 01:33:28 -08:00

intr_control.hh

arch: Header clean up for NOISA resurrection

2013-09-04 13:22:55 -04:00

IntrControl.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

nativetrace.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

nativetrace.hh

cpu: Remove all notion that we know when the cpu is misspeculating.

2015-01-25 07:22:26 -05:00

op_class.hh

CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.

2010-11-15 14:04:04 -06:00

pc_event.cc

arm: Enable support for triggering a sim panic on kernel panics

2013-04-22 13:20:31 -04:00

pc_event.hh

arm: Enable support for triggering a sim panic on kernel panics

2013-04-22 13:20:31 -04:00

profile.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

profile.hh

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

quiesce_event.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

quiesce_event.hh

clang: Enable compiling gem5 using clang 2.9 and 3.0

2012-01-31 12:05:52 -05:00

reg_class.cc

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

reg_class.hh

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

SConscript

cpu: add support for outputing a protobuf formatted CPU trace

2015-02-16 03:32:38 -05:00

simple_thread.cc

arm: Fixes based on UBSan and static analysis

2014-11-14 03:53:51 -05:00

simple_thread.hh

arch: Make readMiscRegNoEffect const throughout

2015-02-16 03:33:28 -05:00

smt.hh

includes: fix up code after sorting

2011-04-15 10:44:14 -07:00

static_inst_fwd.hh

cpu: Don't forward declare RefCountingPtr

2014-08-13 06:57:26 -04:00

static_inst.cc

cpu: Add flag name printing to StaticInst

2014-05-09 18:58:47 -04:00

static_inst.hh

cpu: o3 register renaming request handling improved

2015-03-02 04:00:38 -05:00

StaticInstFlags.py

cpu: Add flag name printing to StaticInst

2014-05-09 18:58:47 -04:00

thread_context.cc

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

thread_context.hh

arch: Make readMiscRegNoEffect const throughout

2015-02-16 03:33:28 -05:00

thread_state.cc

arm: Fixes based on UBSan and static analysis

2014-11-14 03:53:51 -05:00

thread_state.hh

cpu, arm: Allow the specification of a socket field

2014-05-09 18:58:46 -04:00

timebuf.hh

cpu: Timebuf const accessors

2014-05-09 18:58:47 -04:00

timing_expr.cc

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

timing_expr.hh

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

TimingExpr.py

cpu: `Minor' in-order CPU model

2014-07-23 16:09:04 -05:00

translation.hh

sim: Move the BaseTLB to src/arch/generic/

2015-02-11 10:23:27 -05:00