Anthony Gutierrez 332adcdd1a Sim: Fix Simulation.py to allow more than 1 core for standard switching. ...

This patch moves the assignment of testsys.switch_cpus, testsys.switch_cpus_1,
switch_cpu_list, and switch_cpu_list1 outside of the for loop so they are
assigned only once, after switch_cpus and switch_cpus_1 are constructed.

2011-04-04 11:42:31 -05:00

..

Benchmarks.py

Configs: Explicitly import env in Benchmarks.py

2011-02-24 02:14:45 -08:00

CacheConfig.py

configs: cache: add cache line size option

2011-02-23 14:26:55 -05:00

Caches.py

Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.

2011-03-17 19:20:19 -05:00

cpu2000.py

ARM: fix sizes of structs for ARM Linux

2010-06-02 12:58:17 -05:00

FSConfig.py

ARM: Bare metal system should have 256MB of RAM.

2011-03-17 19:20:20 -05:00

Options.py

configs: cache: add cache line size option

2011-02-23 14:26:55 -05:00

Simulation.py

Sim: Fix Simulation.py to allow more than 1 core for standard switching.

2011-04-04 11:42:31 -05:00

SysPaths.py

make rcS files read from the m5 source directory, not /dist.

2006-11-08 14:10:25 -05:00