330a5f7bad
With this commit we replace every TLB pointer stored in the cpu model with a BaseMMU pointer. JIRA: https://gem5.atlassian.net/browse/GEM5-790 Change-Id: I4932a32f68582b25cd252b5420b54d6a40ee15b8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34976 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
54 lines
2.3 KiB
Python
54 lines
2.3 KiB
Python
# Copyright (c) 2008 The Hewlett-Packard Development Company
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from __future__ import print_function
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from m5.defines import buildEnv
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from m5.params import *
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from m5.objects.BaseCPU import BaseCPU
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from m5.objects.DummyChecker import DummyChecker
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from m5.objects.BranchPredictor import *
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class BaseSimpleCPU(BaseCPU):
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type = 'BaseSimpleCPU'
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abstract = True
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cxx_header = "cpu/simple/base.hh"
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def addCheckerCpu(self):
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if buildEnv['TARGET_ISA'] in ['arm']:
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from m5.objects.ArmTLB import ArmMMU
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self.checker = DummyChecker(workload = self.workload)
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self.checker.mmu = ArmMMU()
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self.checker.mmu.itb.size = self.mmu.itb.size
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self.checker.mmu.dtb.size = self.mmu.dtb.size
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else:
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print("ERROR: Checker only supported under ARM ISA!")
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exit(1)
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branchPred = Param.BranchPredictor(NULL, "Branch Predictor")
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