4dd099ba3d
As part of recent decisions regarding namespace naming conventions, all namespaces will be changed to snake case. ::Enums became ::enums. Change-Id: I39b5fb48817ad16abbac92f6254284b37fc90c40 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45420 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
493 lines
15 KiB
C++
493 lines
15 KiB
C++
/*
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* Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __GPU_DYN_INST_HH__
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#define __GPU_DYN_INST_HH__
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#include <cstdint>
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#include <memory>
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#include <string>
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#include "base/amo.hh"
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#include "base/logging.hh"
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#include "base/trace.hh"
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#include "debug/GPUMem.hh"
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#include "enums/StorageClassType.hh"
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#include "gpu-compute/compute_unit.hh"
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#include "gpu-compute/gpu_exec_context.hh"
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#include "gpu-compute/operand_info.hh"
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class GPUStaticInst;
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template<typename T>
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class AtomicOpCAS : public TypedAtomicOpFunctor<T>
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{
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public:
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T c;
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T s;
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ComputeUnit *computeUnit;
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AtomicOpCAS(T _c, T _s, ComputeUnit *compute_unit)
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: c(_c), s(_s), computeUnit(compute_unit) { }
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void
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execute(T *b)
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{
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computeUnit->stats.numCASOps++;
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if (*b == c) {
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*b = s;
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} else {
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computeUnit->stats.numFailedCASOps++;
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}
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}
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AtomicOpFunctor* clone () { return new AtomicOpCAS(c, s, computeUnit); }
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};
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class RegisterOperandInfo
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{
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public:
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RegisterOperandInfo() = delete;
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RegisterOperandInfo(int op_idx, int num_dwords,
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const std::vector<int> &virt_indices,
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const std::vector<int> &phys_indices)
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: opIdx(op_idx), numDWORDs(num_dwords), virtIndices(virt_indices),
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physIndices(phys_indices)
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{
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}
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/**
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* The number of registers required to store this operand.
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*/
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int numRegisters() const { return numDWORDs / TheGpuISA::RegSizeDWords; }
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int operandIdx() const { return opIdx; }
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/**
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* We typically only need the first virtual register for the operand
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* regardless of its size.
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*/
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int virtIdx(int reg_num=0) const { return virtIndices.at(reg_num); }
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private:
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/**
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* Index of this operand within the set of its parent instruction's
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* operand list.
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*/
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const int opIdx;
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/**
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* Size of this operand in DWORDs.
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*/
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const int numDWORDs;
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const std::vector<int> virtIndices;
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const std::vector<int> physIndices;
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};
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class GPUDynInst : public GPUExecContext
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{
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public:
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GPUDynInst(ComputeUnit *_cu, Wavefront *_wf, GPUStaticInst *static_inst,
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uint64_t instSeqNum);
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~GPUDynInst();
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void execute(GPUDynInstPtr gpuDynInst);
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const std::vector<OperandInfo>& srcVecRegOperands() const;
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const std::vector<OperandInfo>& dstVecRegOperands() const;
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const std::vector<OperandInfo>& srcScalarRegOperands() const;
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const std::vector<OperandInfo>& dstScalarRegOperands() const;
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int numSrcRegOperands();
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int numDstRegOperands();
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int numSrcVecRegOperands() const;
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int numDstVecRegOperands() const;
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int maxSrcVecRegOperandSize();
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int numSrcVecDWords();
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int numDstVecDWords();
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int numSrcScalarRegOperands() const;
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int numDstScalarRegOperands() const;
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int maxSrcScalarRegOperandSize();
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int numSrcScalarDWords();
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int numDstScalarDWords();
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int maxOperandSize();
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int getNumOperands() const;
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bool hasSourceSgpr() const;
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bool hasDestinationSgpr() const;
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bool hasSourceVgpr() const;
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bool hasDestinationVgpr() const;
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// returns true if the string "opcodeStr" is found in the
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// opcode of the instruction
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bool isOpcode(const std::string& opcodeStr) const;
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bool isOpcode(const std::string& opcodeStr,
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const std::string& extStr) const;
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const std::string &disassemble() const;
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InstSeqNum seqNum() const;
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enums::StorageClassType executedAs();
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// virtual address for scalar memory operations
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Addr scalarAddr;
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// virtual addressies for vector memory operations
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std::vector<Addr> addr;
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Addr pAddr;
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// vector data to get written
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uint8_t *d_data;
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// scalar data to be transferred
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uint8_t *scalar_data;
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// Additional data (for atomics)
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uint8_t *a_data;
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// Additional data (for atomics)
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uint8_t *x_data;
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// The execution mask
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VectorMask exec_mask;
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// SIMD where the WF of the memory instruction has been mapped to
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int simdId;
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// unique id of the WF where the memory instruction belongs to
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int wfDynId;
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// The kernel id of the requesting wf
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int kern_id;
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// The CU id of the requesting wf
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int cu_id;
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// The workgroup id of the requesting wf
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int wg_id;
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// HW slot id where the WF is mapped to inside a SIMD unit
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int wfSlotId;
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// execution pipeline id where the memory instruction has been scheduled
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int execUnitId;
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// The execution time of this operation
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Tick time;
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// The latency of this operation
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WaitClass latency;
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// Initiate the specified memory operation, by creating a
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// memory request and sending it off to the memory system.
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void initiateAcc(GPUDynInstPtr gpuDynInst);
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// Complete the specified memory operation, by writing
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// value back to the RF in the case of a load or atomic
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// return or, in the case of a store, we do nothing
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void completeAcc(GPUDynInstPtr gpuDynInst);
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void updateStats();
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GPUStaticInst* staticInstruction() { return _staticInst; }
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TheGpuISA::ScalarRegU32 srcLiteral() const;
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bool isALU() const;
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bool isBranch() const;
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bool isCondBranch() const;
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bool isNop() const;
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bool isReturn() const;
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bool isEndOfKernel() const;
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bool isKernelLaunch() const;
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bool isSDWAInst() const;
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bool isDPPInst() const;
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bool isUnconditionalJump() const;
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bool isSpecialOp() const;
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bool isWaitcnt() const;
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bool isSleep() const;
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bool isBarrier() const;
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bool isMemSync() const;
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bool isMemRef() const;
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bool isFlat() const;
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bool isLoad() const;
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bool isStore() const;
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bool isAtomic() const;
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bool isAtomicNoRet() const;
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bool isAtomicRet() const;
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bool isScalar() const;
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bool isVector() const;
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bool readsSCC() const;
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bool writesSCC() const;
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bool readsVCC() const;
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bool writesVCC() const;
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bool readsExec() const;
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bool writesExec() const;
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bool readsMode() const;
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bool writesMode() const;
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bool ignoreExec() const;
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bool readsFlatScratch() const;
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bool writesFlatScratch() const;
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bool readsExecMask() const;
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bool writesExecMask() const;
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bool isAtomicAnd() const;
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bool isAtomicOr() const;
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bool isAtomicXor() const;
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bool isAtomicCAS() const;
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bool isAtomicExch() const;
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bool isAtomicAdd() const;
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bool isAtomicSub() const;
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bool isAtomicInc() const;
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bool isAtomicDec() const;
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bool isAtomicMax() const;
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bool isAtomicMin() const;
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bool isArgLoad() const;
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bool isGlobalMem() const;
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bool isLocalMem() const;
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bool isArgSeg() const;
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bool isGlobalSeg() const;
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bool isGroupSeg() const;
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bool isKernArgSeg() const;
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bool isPrivateSeg() const;
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bool isReadOnlySeg() const;
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bool isSpillSeg() const;
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bool isGloballyCoherent() const;
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bool isSystemCoherent() const;
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bool isF16() const;
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bool isF32() const;
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bool isF64() const;
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bool isFMA() const;
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bool isMAC() const;
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bool isMAD() const;
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// for FLAT memory ops. check the segment address
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// against the APE registers to see if it falls
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// within one of the APE ranges for LDS/SCRATCH/GPUVM.
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// if it does not fall into one of the three APEs, it
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// will be a regular global access.
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void doApertureCheck(const VectorMask &mask);
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// Function to resolve a flat accesses during execution stage.
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void resolveFlatSegment(const VectorMask &mask);
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template<typename c0> AtomicOpFunctorPtr
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makeAtomicOpFunctor(c0 *reg0, c0 *reg1)
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{
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if (isAtomicAnd()) {
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return std::make_unique<AtomicOpAnd<c0>>(*reg0);
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} else if (isAtomicOr()) {
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return std::make_unique<AtomicOpOr<c0>>(*reg0);
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} else if (isAtomicXor()) {
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return std::make_unique<AtomicOpXor<c0>>(*reg0);
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} else if (isAtomicCAS()) {
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return std::make_unique<AtomicOpCAS<c0>>(*reg0, *reg1, cu);
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} else if (isAtomicExch()) {
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return std::make_unique<AtomicOpExch<c0>>(*reg0);
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} else if (isAtomicAdd()) {
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return std::make_unique<AtomicOpAdd<c0>>(*reg0);
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} else if (isAtomicSub()) {
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return std::make_unique<AtomicOpSub<c0>>(*reg0);
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} else if (isAtomicInc()) {
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return std::make_unique<AtomicOpInc<c0>>();
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} else if (isAtomicDec()) {
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return std::make_unique<AtomicOpDec<c0>>();
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} else if (isAtomicMax()) {
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return std::make_unique<AtomicOpMax<c0>>(*reg0);
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} else if (isAtomicMin()) {
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return std::make_unique<AtomicOpMin<c0>>(*reg0);
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} else {
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fatal("Unrecognized atomic operation");
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}
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}
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void
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setRequestFlags(RequestPtr req) const
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{
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if (isGloballyCoherent()) {
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req->setCacheCoherenceFlags(Request::GLC_BIT);
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}
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if (isSystemCoherent()) {
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req->setCacheCoherenceFlags(Request::SLC_BIT);
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}
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if (isAtomicRet()) {
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req->setFlags(Request::ATOMIC_RETURN_OP);
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} else if (isAtomicNoRet()) {
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req->setFlags(Request::ATOMIC_NO_RETURN_OP);
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}
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if (isMemSync()) {
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// the path for kernel launch and kernel end is different
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// from non-kernel mem sync.
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assert(!isKernelLaunch());
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assert(!isEndOfKernel());
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// must be wbinv inst if not kernel launch/end
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req->setCacheCoherenceFlags(Request::INV_L1);
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}
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}
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// reset the number of pending memory requests for all lanes
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void
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resetEntireStatusVector()
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{
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assert(statusVector.size() == TheGpuISA::NumVecElemPerVecReg);
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for (int lane = 0; lane < TheGpuISA::NumVecElemPerVecReg; ++lane) {
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resetStatusVector(lane);
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}
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}
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// reset the number of pending memory requests for the inputted lane
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void
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resetStatusVector(int lane)
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{
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setStatusVector(lane, 0);
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}
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// set the number of pending memory requests for the inputted lane
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void
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setStatusVector(int lane, int newVal)
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{
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// currently we can have up to 2 memory requests per lane (if the
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// lane's request goes across multiple cache lines)
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assert((newVal >= 0) && (newVal <= 2));
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statusVector[lane] = newVal;
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}
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// subtracts the number of pending memory requests for the inputted lane
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// by 1
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void
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decrementStatusVector(int lane)
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{
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// this lane may have multiple requests, so only subtract one for
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// this request
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assert(statusVector[lane] >= 1);
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statusVector[lane]--;
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}
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// return the current number of pending memory requests for the inputted
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// lane
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int
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getLaneStatus(int lane) const
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{
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return statusVector[lane];
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}
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// returns true if all memory requests from all lanes have been received,
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// else returns false
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bool
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allLanesZero() const
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{
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// local variables
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bool allZero = true;
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// iterate over all lanes, checking the number of pending memory
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// requests they have
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for (int lane = 0; lane < TheGpuISA::NumVecElemPerVecReg; ++lane) {
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// if any lane still has pending requests, return false
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if (statusVector[lane] > 0) {
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DPRINTF(GPUMem, "CU%d: WF[%d][%d]: lane: %d has %d pending "
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"request(s) for %#x\n", cu_id, simdId, wfSlotId, lane,
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statusVector[lane], addr[lane]);
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allZero = false;
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}
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}
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if (allZero) {
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DPRINTF(GPUMem, "CU%d: WF[%d][%d]: all lanes have no pending"
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" requests for %#x\n", cu_id, simdId, wfSlotId, addr[0]);
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}
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return allZero;
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}
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// returns a string representing the current state of the statusVector
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std::string
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printStatusVector() const
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{
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std::string statusVec_str = "[";
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// iterate over all lanes, adding the current number of pending
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// requests for this lane to the string
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for (int lane = 0; lane < TheGpuISA::NumVecElemPerVecReg; ++lane) {
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statusVec_str += std::to_string(statusVector[lane]);
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}
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statusVec_str += "]";
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return statusVec_str;
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}
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// Map returned packets and the addresses they satisfy with which lane they
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// were requested from
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typedef std::unordered_map<Addr, std::vector<int>> StatusVector;
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StatusVector memStatusVector;
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// Track the status of memory requests per lane, an int per lane to allow
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// unaligned accesses
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std::vector<int> statusVector;
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// for ld_v# or st_v#
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std::vector<int> tlbHitLevel;
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// for misaligned scalar ops we track the number
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// of outstanding reqs here
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int numScalarReqs;
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Tick getAccessTime() const { return accessTime; }
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void setAccessTime(Tick currentTime) { accessTime = currentTime; }
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void profileRoundTripTime(Tick currentTime, int hopId);
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std::vector<Tick> getRoundTripTime() const { return roundTripTime; }
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void profileLineAddressTime(Addr addr, Tick currentTime, int hopId);
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const std::map<Addr, std::vector<Tick>>& getLineAddressTime() const
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{ return lineAddressTime; }
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// inst used to save/restore a wavefront context
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bool isSaveRestore;
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private:
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GPUStaticInst *_staticInst;
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const InstSeqNum _seqNum;
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int maxSrcVecRegOpSize;
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int maxSrcScalarRegOpSize;
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// the time the request was started
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Tick accessTime = -1;
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// hold the tick when the instruction arrives at certain hop points
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// on it's way to main memory
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std::vector<Tick> roundTripTime;
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// hold each cache block address for the instruction and a vector
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// to hold the tick when the block arrives at certain hop points
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std::map<Addr, std::vector<Tick>> lineAddressTime;
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};
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#endif // __GPU_DYN_INST_HH__
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