921a72f4f3
Change-Id: I439d64d01950463747446a8177086eb276b8db55 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25443 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
127 lines
3.5 KiB
C++
127 lines
3.5 KiB
C++
/*
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* Copyright (c) 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_PACKET_ACCESS_HH__
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#define __MEM_PACKET_ACCESS_HH__
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#include "mem/packet.hh"
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#include "sim/byteswap.hh"
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template <typename T>
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inline T
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Packet::getRaw() const
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{
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assert(flags.isSet(STATIC_DATA|DYNAMIC_DATA));
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assert(sizeof(T) <= size);
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return *(T*)data;
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}
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template <typename T>
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inline void
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Packet::setRaw(T v)
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{
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assert(flags.isSet(STATIC_DATA|DYNAMIC_DATA));
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assert(sizeof(T) <= size);
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*(T*)data = v;
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}
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template <typename T>
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inline T
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Packet::getBE() const
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{
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return betoh(getRaw<T>());
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}
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template <typename T>
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inline T
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Packet::getLE() const
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{
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return letoh(getRaw<T>());
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}
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template <typename T>
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inline T
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Packet::get(ByteOrder endian) const
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{
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switch (endian) {
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case BigEndianByteOrder:
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return getBE<T>();
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case LittleEndianByteOrder:
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return getLE<T>();
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default:
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panic("Illegal byte order in Packet::get()\n");
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};
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}
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template <typename T>
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inline void
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Packet::setBE(T v)
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{
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setRaw(htobe(v));
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}
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template <typename T>
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inline void
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Packet::setLE(T v)
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{
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setRaw(htole(v));
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}
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template <typename T>
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inline void
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Packet::set(T v, ByteOrder endian)
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{
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switch (endian) {
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case BigEndianByteOrder:
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return setBE<T>(v);
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case LittleEndianByteOrder:
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return setLE<T>(v);
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default:
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panic("Illegal byte order in Packet::set()\n");
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};
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}
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#endif //__MEM_PACKET_ACCESS_HH__
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