2fbbdad618
This commit converts `gem5::loader::Symbol` to a full class with private members, enforcing encapsulation. Until now client code has been able to (and does) access members directly. This change will enable class invariants to be enforced via accessor methods. Change-Id: Ia0b5b080d4f656637a211808e13dce1ddca74541 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
1076 lines
35 KiB
C++
1076 lines
35 KiB
C++
/*
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* Copyright (c) 2011-2012,2016-2017, 2019-2020 Arm Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2011 Regents of the University of California
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* Copyright (c) 2013 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/base.hh"
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#include <iostream>
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#include <sstream>
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#include <string>
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#include "arch/generic/decoder.hh"
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#include "arch/generic/isa.hh"
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#include "arch/generic/tlb.hh"
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#include "base/cprintf.hh"
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#include "base/loader/symtab.hh"
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#include "base/logging.hh"
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#include "base/output.hh"
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#include "base/trace.hh"
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#include "cpu/checker/cpu.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Mwait.hh"
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#include "debug/SyscallVerbose.hh"
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#include "debug/Thread.hh"
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#include "mem/page_table.hh"
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#include "params/BaseCPU.hh"
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#include "sim/clocked_object.hh"
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#include "sim/full_system.hh"
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#include "sim/process.hh"
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#include "sim/root.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_exit.hh"
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#include "sim/system.hh"
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// Hack
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#include "sim/stat_control.hh"
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namespace gem5
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{
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std::unique_ptr<BaseCPU::GlobalStats> BaseCPU::globalStats;
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std::vector<BaseCPU *> BaseCPU::cpuList;
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// This variable reflects the max number of threads in any CPU. Be
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// careful to only use it once all the CPUs that you care about have
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// been initialized
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int maxThreadsPerCPU = 1;
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CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival)
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: Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0),
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cpu(_cpu), _repeatEvent(true)
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{
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if (_interval)
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cpu->schedule(this, curTick() + _interval);
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}
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void
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CPUProgressEvent::process()
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{
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Counter temp = cpu->totalOps();
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if (_repeatEvent)
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cpu->schedule(this, curTick() + _interval);
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if (cpu->switchedOut()) {
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return;
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}
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#ifndef NDEBUG
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double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod());
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DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
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"%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst,
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ipc);
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ipc = 0.0;
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#else
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cprintf("%lli: %s progress event, total committed:%i, progress insts "
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"committed: %lli\n", curTick(), cpu->name(), temp,
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temp - lastNumInst);
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#endif
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lastNumInst = temp;
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}
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const char *
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CPUProgressEvent::description() const
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{
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return "CPU Progress";
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}
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BaseCPU::BaseCPU(const Params &p, bool is_checker)
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: ClockedObject(p), instCnt(0), _cpuId(p.cpu_id), _socketId(p.socket_id),
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_instRequestorId(p.system->getRequestorId(this, "inst")),
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_dataRequestorId(p.system->getRequestorId(this, "data")),
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_taskId(context_switch_task_id::Unknown), _pid(invldPid),
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_switchedOut(p.switched_out), _cacheLineSize(p.system->cacheLineSize()),
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modelResetPort(p.name + ".model_reset"),
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interrupts(p.interrupts), numThreads(p.numThreads), system(p.system),
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previousCycle(0), previousState(CPU_STATE_SLEEP),
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functionTraceStream(nullptr), currentFunctionStart(0),
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currentFunctionEnd(0), functionEntryTick(0),
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baseStats(this),
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addressMonitor(p.numThreads),
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syscallRetryLatency(p.syscallRetryLatency),
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pwrGatingLatency(p.pwr_gating_latency),
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powerGatingOnIdle(p.power_gating_on_idle),
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enterPwrGatingEvent([this]{ enterPwrGating(); }, name())
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{
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// if Python did not provide a valid ID, do it here
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if (_cpuId == -1 ) {
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_cpuId = cpuList.size();
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}
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// add self to global list of CPUs
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cpuList.push_back(this);
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DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n",
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_cpuId, _socketId);
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if (numThreads > maxThreadsPerCPU)
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maxThreadsPerCPU = numThreads;
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functionTracingEnabled = false;
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if (p.function_trace) {
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const std::string fname = csprintf("ftrace.%s", name());
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functionTraceStream = simout.findOrCreate(fname)->stream();
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currentFunctionStart = currentFunctionEnd = 0;
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functionEntryTick = p.function_trace_start;
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if (p.function_trace_start == 0) {
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functionTracingEnabled = true;
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} else {
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Event *event = new EventFunctionWrapper(
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[this]{ enableFunctionTrace(); }, name(), true);
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schedule(event, p.function_trace_start);
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}
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}
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tracer = params().tracer;
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if (params().isa.size() != numThreads) {
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fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
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"of threads (%i).\n", params().isa.size(), numThreads);
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}
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if (!FullSystem && params().workload.size() != numThreads) {
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fatal("Number of processes (cpu.workload) (%i) assigned to the CPU "
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"does not equal number of threads (%i).\n",
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params().workload.size(), numThreads);
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}
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modelResetPort.onChange([this](const bool &new_val) {
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setReset(new_val);
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});
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// create a stat group object for each thread on this core
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fetchStats.reserve(numThreads);
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executeStats.reserve(numThreads);
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commitStats.reserve(numThreads);
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for (int i = 0; i < numThreads; i++) {
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// create fetchStat object for thread i and set rate formulas
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FetchCPUStats* fetchStatptr = new FetchCPUStats(this, i);
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fetchStatptr->fetchRate = fetchStatptr->numInsts / baseStats.numCycles;
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fetchStatptr->branchRate = fetchStatptr->numBranches /
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baseStats.numCycles;
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fetchStats.emplace_back(fetchStatptr);
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// create executeStat object for thread i and set rate formulas
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ExecuteCPUStats* executeStatptr = new ExecuteCPUStats(this, i);
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executeStatptr->instRate = executeStatptr->numInsts /
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baseStats.numCycles;
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executeStats.emplace_back(executeStatptr);
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// create commitStat object for thread i and set ipc, cpi formulas
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CommitCPUStats* commitStatptr = new CommitCPUStats(this, i);
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commitStatptr->ipc = commitStatptr->numInsts / baseStats.numCycles;
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commitStatptr->cpi = baseStats.numCycles / commitStatptr->numInsts;
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commitStats.emplace_back(commitStatptr);
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}
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}
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void
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BaseCPU::enableFunctionTrace()
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{
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functionTracingEnabled = true;
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}
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BaseCPU::~BaseCPU()
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{
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}
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void
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BaseCPU::postInterrupt(ThreadID tid, int int_num, int index)
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{
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interrupts[tid]->post(int_num, index);
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// Only wake up syscall emulation if it is not waiting on a futex.
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// This is to model the fact that instructions such as ARM SEV
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// should wake up a WFE sleep, but not a futex syscall WAIT.
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if (FullSystem || !system->futexMap.is_waiting(threadContexts[tid]))
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wakeup(tid);
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}
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void
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BaseCPU::armMonitor(ThreadID tid, Addr address)
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{
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assert(tid < numThreads);
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AddressMonitor &monitor = addressMonitor[tid];
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monitor.armed = true;
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monitor.vAddr = address;
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monitor.pAddr = 0x0;
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DPRINTF(Mwait, "[tid:%d] Armed monitor (vAddr=0x%lx)\n", tid, address);
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}
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bool
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BaseCPU::mwait(ThreadID tid, PacketPtr pkt)
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{
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assert(tid < numThreads);
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AddressMonitor &monitor = addressMonitor[tid];
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if (!monitor.gotWakeup) {
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Addr block_size = cacheLineSize();
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Addr mask = ~(block_size - 1);
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assert(pkt->req->hasPaddr());
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monitor.pAddr = pkt->getAddr() & mask;
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monitor.waiting = true;
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DPRINTF(Mwait, "[tid:%d] mwait called (vAddr=0x%lx, "
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"line's paddr=0x%lx)\n", tid, monitor.vAddr, monitor.pAddr);
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return true;
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} else {
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monitor.gotWakeup = false;
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return false;
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}
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}
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void
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BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
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{
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assert(tid < numThreads);
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AddressMonitor &monitor = addressMonitor[tid];
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RequestPtr req = std::make_shared<Request>();
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Addr addr = monitor.vAddr;
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Addr block_size = cacheLineSize();
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Addr mask = ~(block_size - 1);
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int size = block_size;
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//The address of the next line if it crosses a cache line boundary.
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Addr secondAddr = roundDown(addr + size - 1, block_size);
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if (secondAddr > addr)
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size = secondAddr - addr;
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req->setVirt(addr, size, 0x0, dataRequestorId(),
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tc->pcState().instAddr());
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// translate to physical address
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Fault fault = mmu->translateAtomic(req, tc, BaseMMU::Read);
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assert(fault == NoFault);
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monitor.pAddr = req->getPaddr() & mask;
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monitor.waiting = true;
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DPRINTF(Mwait, "[tid:%d] mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n",
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tid, monitor.vAddr, monitor.pAddr);
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}
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void
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BaseCPU::init()
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{
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// Set up instruction-count-based termination events, if any. This needs
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// to happen after threadContexts has been constructed.
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if (params().max_insts_any_thread != 0) {
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scheduleInstStopAnyThread(params().max_insts_any_thread);
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}
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// Set up instruction-count-based termination events for SimPoints
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// Typically, there are more than one action points.
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// Simulation.py is responsible to take the necessary actions upon
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// exitting the simulation loop.
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if (!params().simpoint_start_insts.empty()) {
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scheduleSimpointsInstStop(params().simpoint_start_insts);
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}
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if (params().max_insts_all_threads != 0) {
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std::string cause = "all threads reached the max instruction count";
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// allocate & initialize shared downcounter: each event will
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// decrement this when triggered; simulation will terminate
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// when counter reaches 0
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int *counter = new int;
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*counter = numThreads;
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for (ThreadID tid = 0; tid < numThreads; ++tid) {
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Event *event = new CountedExitEvent(cause, *counter);
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threadContexts[tid]->scheduleInstCountEvent(
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event, params().max_insts_all_threads);
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}
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}
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if (!params().switched_out) {
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registerThreadContexts();
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verifyMemoryMode();
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}
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}
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void
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BaseCPU::startup()
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{
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if (params().progress_interval) {
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new CPUProgressEvent(this, params().progress_interval);
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}
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if (_switchedOut)
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powerState->set(enums::PwrState::OFF);
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// Assumption CPU start to operate instantaneously without any latency
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if (powerState->get() == enums::PwrState::UNDEFINED)
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powerState->set(enums::PwrState::ON);
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}
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probing::PMUUPtr
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BaseCPU::pmuProbePoint(const char *name)
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{
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probing::PMUUPtr ptr;
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ptr.reset(new probing::PMU(getProbeManager(), name));
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return ptr;
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}
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void
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BaseCPU::regProbePoints()
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{
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ppAllCycles = pmuProbePoint("Cycles");
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ppActiveCycles = pmuProbePoint("ActiveCycles");
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ppRetiredInsts = pmuProbePoint("RetiredInsts");
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ppRetiredInstsPC = pmuProbePoint("RetiredInstsPC");
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ppRetiredLoads = pmuProbePoint("RetiredLoads");
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ppRetiredStores = pmuProbePoint("RetiredStores");
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ppRetiredBranches = pmuProbePoint("RetiredBranches");
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ppSleeping = new ProbePointArg<bool>(this->getProbeManager(),
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"Sleeping");
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}
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void
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BaseCPU::probeInstCommit(const StaticInstPtr &inst, Addr pc)
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{
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if (!inst->isMicroop() || inst->isLastMicroop()) {
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ppRetiredInsts->notify(1);
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ppRetiredInstsPC->notify(pc);
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}
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if (inst->isLoad())
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ppRetiredLoads->notify(1);
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if (inst->isStore() || inst->isAtomic())
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ppRetiredStores->notify(1);
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if (inst->isControl())
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ppRetiredBranches->notify(1);
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}
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BaseCPU::
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BaseCPUStats::BaseCPUStats(statistics::Group *parent)
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: statistics::Group(parent),
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ADD_STAT(numCycles, statistics::units::Cycle::get(),
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"Number of cpu cycles simulated"),
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ADD_STAT(cpi, statistics::units::Rate<
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statistics::units::Cycle, statistics::units::Count>::get(),
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"CPI: cycles per instruction (core level)"),
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ADD_STAT(ipc, statistics::units::Rate<
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statistics::units::Count, statistics::units::Cycle>::get(),
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"IPC: instructions per cycle (core level)"),
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ADD_STAT(numWorkItemsStarted, statistics::units::Count::get(),
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"Number of work items this cpu started"),
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ADD_STAT(numWorkItemsCompleted, statistics::units::Count::get(),
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"Number of work items this cpu completed")
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{
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cpi.precision(6);
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cpi = numCycles / numInsts;
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ipc.precision(6);
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ipc = numInsts / numCycles;
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}
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void
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BaseCPU::regStats()
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{
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ClockedObject::regStats();
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if (!globalStats) {
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/* We need to construct the global CPU stat structure here
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* since it needs a pointer to the Root object. */
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globalStats.reset(new GlobalStats(Root::root()));
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}
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using namespace statistics;
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int size = threadContexts.size();
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if (size > 1) {
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for (int i = 0; i < size; ++i) {
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std::stringstream namestr;
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ccprintf(namestr, "%s.ctx%d", name(), i);
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threadContexts[i]->regStats(namestr.str());
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}
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} else if (size == 1)
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threadContexts[0]->regStats(name());
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}
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Port &
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BaseCPU::getPort(const std::string &if_name, PortID idx)
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{
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// Get the right port based on name. This applies to all the
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// subclasses of the base CPU and relies on their implementation
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// of getDataPort and getInstPort.
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if (if_name == "dcache_port")
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return getDataPort();
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else if (if_name == "icache_port")
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return getInstPort();
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else if (if_name == "model_reset")
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return modelResetPort;
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else
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return ClockedObject::getPort(if_name, idx);
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}
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void
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BaseCPU::registerThreadContexts()
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{
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assert(system->multiThread || numThreads == 1);
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fatal_if(interrupts.size() != numThreads,
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"CPU %s has %i interrupt controllers, but is expecting one "
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"per thread (%i)\n",
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name(), interrupts.size(), numThreads);
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for (ThreadID tid = 0; tid < threadContexts.size(); ++tid) {
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ThreadContext *tc = threadContexts[tid];
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system->registerThreadContext(tc);
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if (!FullSystem)
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tc->getProcessPtr()->assignThreadContext(tc->contextId());
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interrupts[tid]->setThreadContext(tc);
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tc->getIsaPtr()->setThreadContext(tc);
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}
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}
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void
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BaseCPU::deschedulePowerGatingEvent()
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{
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if (enterPwrGatingEvent.scheduled()){
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deschedule(enterPwrGatingEvent);
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}
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}
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void
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BaseCPU::schedulePowerGatingEvent()
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{
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for (auto tc : threadContexts) {
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if (tc->status() == ThreadContext::Active)
|
|
return;
|
|
}
|
|
|
|
if (powerState->get() == enums::PwrState::CLK_GATED &&
|
|
powerGatingOnIdle) {
|
|
assert(!enterPwrGatingEvent.scheduled());
|
|
// Schedule a power gating event when clock gated for the specified
|
|
// amount of time
|
|
schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency));
|
|
}
|
|
}
|
|
|
|
int
|
|
BaseCPU::findContext(ThreadContext *tc)
|
|
{
|
|
ThreadID size = threadContexts.size();
|
|
for (ThreadID tid = 0; tid < size; ++tid) {
|
|
if (tc == threadContexts[tid])
|
|
return tid;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
BaseCPU::activateContext(ThreadID thread_num)
|
|
{
|
|
if (modelResetPort.state()) {
|
|
DPRINTF(Thread, "CPU in reset, not activating context %d\n",
|
|
threadContexts[thread_num]->contextId());
|
|
return;
|
|
}
|
|
|
|
DPRINTF(Thread, "activate contextId %d\n",
|
|
threadContexts[thread_num]->contextId());
|
|
// Squash enter power gating event while cpu gets activated
|
|
if (enterPwrGatingEvent.scheduled())
|
|
deschedule(enterPwrGatingEvent);
|
|
// For any active thread running, update CPU power state to active (ON)
|
|
powerState->set(enums::PwrState::ON);
|
|
|
|
updateCycleCounters(CPU_STATE_WAKEUP);
|
|
}
|
|
|
|
void
|
|
BaseCPU::suspendContext(ThreadID thread_num)
|
|
{
|
|
DPRINTF(Thread, "suspend contextId %d\n",
|
|
threadContexts[thread_num]->contextId());
|
|
// Check if all threads are suspended
|
|
for (auto t : threadContexts) {
|
|
if (t->status() != ThreadContext::Suspended) {
|
|
return;
|
|
}
|
|
}
|
|
|
|
// All CPU thread are suspended, update cycle count
|
|
updateCycleCounters(CPU_STATE_SLEEP);
|
|
|
|
// All CPU threads suspended, enter lower power state for the CPU
|
|
powerState->set(enums::PwrState::CLK_GATED);
|
|
|
|
// If pwrGatingLatency is set to 0 then this mechanism is disabled
|
|
if (powerGatingOnIdle) {
|
|
// Schedule power gating event when clock gated for pwrGatingLatency
|
|
// cycles
|
|
schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency));
|
|
}
|
|
}
|
|
|
|
void
|
|
BaseCPU::haltContext(ThreadID thread_num)
|
|
{
|
|
updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
|
|
}
|
|
|
|
void
|
|
BaseCPU::enterPwrGating(void)
|
|
{
|
|
powerState->set(enums::PwrState::OFF);
|
|
}
|
|
|
|
void
|
|
BaseCPU::switchOut()
|
|
{
|
|
assert(!_switchedOut);
|
|
_switchedOut = true;
|
|
|
|
// Flush all TLBs in the CPU to avoid having stale translations if
|
|
// it gets switched in later.
|
|
flushTLBs();
|
|
|
|
// Go to the power gating state
|
|
powerState->set(enums::PwrState::OFF);
|
|
}
|
|
|
|
void
|
|
BaseCPU::takeOverFrom(BaseCPU *oldCPU)
|
|
{
|
|
assert(threadContexts.size() == oldCPU->threadContexts.size());
|
|
assert(_cpuId == oldCPU->cpuId());
|
|
assert(_switchedOut);
|
|
assert(oldCPU != this);
|
|
_pid = oldCPU->getPid();
|
|
_taskId = oldCPU->taskId();
|
|
// Take over the power state of the switchedOut CPU
|
|
powerState->set(oldCPU->powerState->get());
|
|
|
|
previousState = oldCPU->previousState;
|
|
previousCycle = oldCPU->previousCycle;
|
|
|
|
_switchedOut = false;
|
|
|
|
ThreadID size = threadContexts.size();
|
|
for (ThreadID i = 0; i < size; ++i) {
|
|
ThreadContext *newTC = threadContexts[i];
|
|
ThreadContext *oldTC = oldCPU->threadContexts[i];
|
|
|
|
newTC->getIsaPtr()->setThreadContext(newTC);
|
|
|
|
newTC->takeOverFrom(oldTC);
|
|
|
|
assert(newTC->contextId() == oldTC->contextId());
|
|
assert(newTC->threadId() == oldTC->threadId());
|
|
system->replaceThreadContext(newTC, newTC->contextId());
|
|
|
|
/* This code no longer works since the zero register (e.g.,
|
|
* r31 on Alpha) doesn't necessarily contain zero at this
|
|
* point.
|
|
if (debug::Context)
|
|
ThreadContext::compare(oldTC, newTC);
|
|
*/
|
|
|
|
newTC->getMMUPtr()->takeOverFrom(oldTC->getMMUPtr());
|
|
|
|
// Checker whether or not we have to transfer CheckerCPU
|
|
// objects over in the switch
|
|
CheckerCPU *old_checker = oldTC->getCheckerCpuPtr();
|
|
CheckerCPU *new_checker = newTC->getCheckerCpuPtr();
|
|
if (old_checker && new_checker) {
|
|
new_checker->getMMUPtr()->takeOverFrom(old_checker->getMMUPtr());
|
|
}
|
|
}
|
|
|
|
interrupts = oldCPU->interrupts;
|
|
for (ThreadID tid = 0; tid < numThreads; tid++) {
|
|
interrupts[tid]->setThreadContext(threadContexts[tid]);
|
|
}
|
|
oldCPU->interrupts.clear();
|
|
|
|
// All CPUs have an instruction and a data port, and the new CPU's
|
|
// ports are dangling while the old CPU has its ports connected
|
|
// already. Unbind the old CPU and then bind the ports of the one
|
|
// we are switching to.
|
|
getInstPort().takeOverFrom(&oldCPU->getInstPort());
|
|
getDataPort().takeOverFrom(&oldCPU->getDataPort());
|
|
|
|
// Switch over the reset line as well, if necessary.
|
|
if (oldCPU->modelResetPort.isConnected())
|
|
modelResetPort.takeOverFrom(&oldCPU->modelResetPort);
|
|
}
|
|
|
|
void
|
|
BaseCPU::setReset(bool state)
|
|
{
|
|
for (auto tc: threadContexts) {
|
|
if (state) {
|
|
// As we enter reset, stop execution.
|
|
tc->quiesce();
|
|
} else {
|
|
// As we leave reset, first reset thread state,
|
|
tc->getIsaPtr()->resetThread();
|
|
// reset the decoder in case it had partially decoded something,
|
|
tc->getDecoderPtr()->reset();
|
|
// flush the TLBs,
|
|
tc->getMMUPtr()->flushAll();
|
|
// Clear any interrupts,
|
|
interrupts[tc->threadId()]->clearAll();
|
|
// and finally reenable execution.
|
|
tc->activate();
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
BaseCPU::flushTLBs()
|
|
{
|
|
for (ThreadID i = 0; i < threadContexts.size(); ++i) {
|
|
ThreadContext &tc(*threadContexts[i]);
|
|
CheckerCPU *checker(tc.getCheckerCpuPtr());
|
|
|
|
tc.getMMUPtr()->flushAll();
|
|
if (checker) {
|
|
checker->getMMUPtr()->flushAll();
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
BaseCPU::serialize(CheckpointOut &cp) const
|
|
{
|
|
SERIALIZE_SCALAR(instCnt);
|
|
|
|
if (!_switchedOut) {
|
|
/* Unlike _pid, _taskId is not serialized, as they are dynamically
|
|
* assigned unique ids that are only meaningful for the duration of
|
|
* a specific run. We will need to serialize the entire taskMap in
|
|
* system. */
|
|
SERIALIZE_SCALAR(_pid);
|
|
|
|
// Serialize the threads, this is done by the CPU implementation.
|
|
for (ThreadID i = 0; i < numThreads; ++i) {
|
|
ScopedCheckpointSection sec(cp, csprintf("xc.%i", i));
|
|
interrupts[i]->serialize(cp);
|
|
serializeThread(cp, i);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
BaseCPU::unserialize(CheckpointIn &cp)
|
|
{
|
|
UNSERIALIZE_SCALAR(instCnt);
|
|
|
|
if (!_switchedOut) {
|
|
UNSERIALIZE_SCALAR(_pid);
|
|
|
|
// Unserialize the threads, this is done by the CPU implementation.
|
|
for (ThreadID i = 0; i < numThreads; ++i) {
|
|
ScopedCheckpointSection sec(cp, csprintf("xc.%i", i));
|
|
interrupts[i]->unserialize(cp);
|
|
unserializeThread(cp, i);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, std::string cause)
|
|
{
|
|
const Tick now(getCurrentInstCount(tid));
|
|
Event *event(new LocalSimLoopExitEvent(cause, 0));
|
|
|
|
threadContexts[tid]->scheduleInstCountEvent(event, now + insts);
|
|
}
|
|
|
|
Tick
|
|
BaseCPU::getCurrentInstCount(ThreadID tid)
|
|
{
|
|
return threadContexts[tid]->getCurrentInstCount();
|
|
}
|
|
|
|
AddressMonitor::AddressMonitor()
|
|
{
|
|
armed = false;
|
|
waiting = false;
|
|
gotWakeup = false;
|
|
}
|
|
|
|
bool
|
|
AddressMonitor::doMonitor(PacketPtr pkt)
|
|
{
|
|
assert(pkt->req->hasPaddr());
|
|
if (armed && waiting) {
|
|
if (pAddr == pkt->getAddr()) {
|
|
DPRINTF(Mwait, "pAddr=0x%lx invalidated: waking up core\n",
|
|
pkt->getAddr());
|
|
waiting = false;
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
|
|
void
|
|
BaseCPU::traceFunctionsInternal(Addr pc)
|
|
{
|
|
if (loader::debugSymbolTable.empty())
|
|
return;
|
|
|
|
// if pc enters different function, print new function symbol and
|
|
// update saved range. Otherwise do nothing.
|
|
if (pc < currentFunctionStart || pc >= currentFunctionEnd) {
|
|
auto it = loader::debugSymbolTable.findNearest(
|
|
pc, currentFunctionEnd);
|
|
|
|
std::string sym_str;
|
|
if (it == loader::debugSymbolTable.end()) {
|
|
// no symbol found: use addr as label
|
|
sym_str = csprintf("%#x", pc);
|
|
currentFunctionStart = pc;
|
|
currentFunctionEnd = pc + 1;
|
|
} else {
|
|
sym_str = it->name();
|
|
currentFunctionStart = it->address();
|
|
}
|
|
|
|
ccprintf(*functionTraceStream, " (%d)\n%d: %s",
|
|
curTick() - functionEntryTick, curTick(), sym_str);
|
|
functionEntryTick = curTick();
|
|
}
|
|
}
|
|
|
|
void
|
|
BaseCPU::scheduleSimpointsInstStop(std::vector<Counter> inst_starts)
|
|
{
|
|
std::string cause = "simpoint starting point found";
|
|
for (size_t i = 0; i < inst_starts.size(); ++i) {
|
|
scheduleInstStop(0, inst_starts[i], cause);
|
|
}
|
|
}
|
|
|
|
void
|
|
BaseCPU::scheduleInstStopAnyThread(Counter max_insts)
|
|
{
|
|
std::string cause = "a thread reached the max instruction count";
|
|
for (ThreadID tid = 0; tid < numThreads; ++tid) {
|
|
scheduleInstStop(tid, max_insts, cause);
|
|
}
|
|
}
|
|
|
|
BaseCPU::GlobalStats::GlobalStats(statistics::Group *parent)
|
|
: statistics::Group(parent),
|
|
ADD_STAT(simInsts, statistics::units::Count::get(),
|
|
"Number of instructions simulated"),
|
|
ADD_STAT(simOps, statistics::units::Count::get(),
|
|
"Number of ops (including micro ops) simulated"),
|
|
ADD_STAT(hostInstRate, statistics::units::Rate<
|
|
statistics::units::Count, statistics::units::Second>::get(),
|
|
"Simulator instruction rate (inst/s)"),
|
|
ADD_STAT(hostOpRate, statistics::units::Rate<
|
|
statistics::units::Count, statistics::units::Second>::get(),
|
|
"Simulator op (including micro ops) rate (op/s)")
|
|
{
|
|
simInsts
|
|
.functor(BaseCPU::numSimulatedInsts)
|
|
.precision(0)
|
|
.prereq(simInsts)
|
|
;
|
|
|
|
simOps
|
|
.functor(BaseCPU::numSimulatedOps)
|
|
.precision(0)
|
|
.prereq(simOps)
|
|
;
|
|
|
|
hostInstRate
|
|
.precision(0)
|
|
.prereq(simInsts)
|
|
;
|
|
|
|
hostOpRate
|
|
.precision(0)
|
|
.prereq(simOps)
|
|
;
|
|
|
|
hostInstRate = simInsts / hostSeconds;
|
|
hostOpRate = simOps / hostSeconds;
|
|
}
|
|
|
|
BaseCPU::
|
|
FetchCPUStats::FetchCPUStats(statistics::Group *parent, int thread_id)
|
|
: statistics::Group(parent, csprintf("fetchStats%i", thread_id).c_str()),
|
|
ADD_STAT(numInsts, statistics::units::Count::get(),
|
|
"Number of instructions fetched (thread level)"),
|
|
ADD_STAT(numOps, statistics::units::Count::get(),
|
|
"Number of ops (including micro ops) fetched (thread level)"),
|
|
ADD_STAT(fetchRate, statistics::units::Rate<
|
|
statistics::units::Count, statistics::units::Cycle>::get(),
|
|
"Number of inst fetches per cycle"),
|
|
ADD_STAT(numBranches, statistics::units::Count::get(),
|
|
"Number of branches fetched"),
|
|
ADD_STAT(branchRate, statistics::units::Ratio::get(),
|
|
"Number of branch fetches per cycle"),
|
|
ADD_STAT(icacheStallCycles, statistics::units::Cycle::get(),
|
|
"ICache total stall cycles"),
|
|
ADD_STAT(numFetchSuspends, statistics::units::Count::get(),
|
|
"Number of times Execute suspended instruction fetching")
|
|
|
|
{
|
|
fetchRate
|
|
.flags(statistics::total);
|
|
|
|
numBranches
|
|
.prereq(numBranches);
|
|
|
|
branchRate
|
|
.flags(statistics::total);
|
|
|
|
icacheStallCycles
|
|
.prereq(icacheStallCycles);
|
|
|
|
}
|
|
|
|
// means it is incremented in a vector indexing and not directly
|
|
BaseCPU::
|
|
ExecuteCPUStats::ExecuteCPUStats(statistics::Group *parent, int thread_id)
|
|
: statistics::Group(parent, csprintf("executeStats%i", thread_id).c_str()),
|
|
ADD_STAT(numInsts, statistics::units::Count::get(),
|
|
"Number of executed instructions"),
|
|
ADD_STAT(numNop, statistics::units::Count::get(),
|
|
"Number of nop insts executed"),
|
|
ADD_STAT(numBranches, statistics::units::Count::get(),
|
|
"Number of branches executed"),
|
|
ADD_STAT(numLoadInsts, statistics::units::Count::get(),
|
|
"Number of load instructions executed"),
|
|
ADD_STAT(numStoreInsts, statistics::units::Count::get(),
|
|
"Number of stores executed"),
|
|
ADD_STAT(instRate, statistics::units::Rate<
|
|
statistics::units::Count, statistics::units::Cycle>::get(),
|
|
"Inst execution rate"),
|
|
ADD_STAT(dcacheStallCycles, statistics::units::Cycle::get(),
|
|
"DCache total stall cycles"),
|
|
ADD_STAT(numCCRegReads, statistics::units::Count::get(),
|
|
"Number of times the CC registers were read"),
|
|
ADD_STAT(numCCRegWrites, statistics::units::Count::get(),
|
|
"Number of times the CC registers were written"),
|
|
ADD_STAT(numFpAluAccesses, statistics::units::Count::get(),
|
|
"Number of float alu accesses"),
|
|
ADD_STAT(numFpRegReads, statistics::units::Count::get(),
|
|
"Number of times the floating registers were read"),
|
|
ADD_STAT(numFpRegWrites, statistics::units::Count::get(),
|
|
"Number of times the floating registers were written"),
|
|
ADD_STAT(numIntAluAccesses, statistics::units::Count::get(),
|
|
"Number of integer alu accesses"),
|
|
ADD_STAT(numIntRegReads, statistics::units::Count::get(),
|
|
"Number of times the integer registers were read"),
|
|
ADD_STAT(numIntRegWrites, statistics::units::Count::get(),
|
|
"Number of times the integer registers were written"),
|
|
ADD_STAT(numMemRefs, statistics::units::Count::get(),
|
|
"Number of memory refs"),
|
|
ADD_STAT(numMiscRegReads, statistics::units::Count::get(),
|
|
"Number of times the Misc registers were read"),
|
|
ADD_STAT(numMiscRegWrites, statistics::units::Count::get(),
|
|
"Number of times the Misc registers were written"),
|
|
ADD_STAT(numVecAluAccesses, statistics::units::Count::get(),
|
|
"Number of vector alu accesses"),
|
|
ADD_STAT(numVecPredRegReads, statistics::units::Count::get(),
|
|
"Number of times the predicate registers were read"),
|
|
ADD_STAT(numVecPredRegWrites, statistics::units::Count::get(),
|
|
"Number of times the predicate registers were written"),
|
|
ADD_STAT(numVecRegReads, statistics::units::Count::get(),
|
|
"Number of times the vector registers were read"),
|
|
ADD_STAT(numVecRegWrites, statistics::units::Count::get(),
|
|
"Number of times the vector registers were written"),
|
|
ADD_STAT(numDiscardedOps, statistics::units::Count::get(),
|
|
"Number of ops (including micro ops) which were discarded before "
|
|
"commit")
|
|
{
|
|
numStoreInsts = numMemRefs - numLoadInsts;
|
|
|
|
dcacheStallCycles
|
|
.prereq(dcacheStallCycles);
|
|
numCCRegReads
|
|
.prereq(numCCRegReads)
|
|
.flags(statistics::nozero);
|
|
numCCRegWrites
|
|
.prereq(numCCRegWrites)
|
|
.flags(statistics::nozero);
|
|
numFpAluAccesses
|
|
.prereq(numFpAluAccesses);
|
|
numFpRegReads
|
|
.prereq(numFpRegReads);
|
|
numIntAluAccesses
|
|
.prereq(numIntAluAccesses);
|
|
numIntRegReads
|
|
.prereq(numIntRegReads);
|
|
numIntRegWrites
|
|
.prereq(numIntRegWrites);
|
|
numMiscRegReads
|
|
.prereq(numMiscRegReads);
|
|
numMiscRegWrites
|
|
.prereq(numMiscRegWrites);
|
|
numVecPredRegReads
|
|
.prereq(numVecPredRegReads);
|
|
numVecPredRegWrites
|
|
.prereq(numVecPredRegWrites);
|
|
numVecRegReads
|
|
.prereq(numVecRegReads);
|
|
numVecRegWrites
|
|
.prereq(numVecRegWrites);
|
|
}
|
|
|
|
BaseCPU::
|
|
CommitCPUStats::CommitCPUStats(statistics::Group *parent, int thread_id)
|
|
: statistics::Group(parent, csprintf("commitStats%i", thread_id).c_str()),
|
|
ADD_STAT(numInsts, statistics::units::Count::get(),
|
|
"Number of instructions committed (thread level)"),
|
|
ADD_STAT(numOps, statistics::units::Count::get(),
|
|
"Number of ops (including micro ops) committed (thread level)"),
|
|
ADD_STAT(numInstsNotNOP, statistics::units::Count::get(),
|
|
"Number of instructions committed excluding NOPs or prefetches"),
|
|
ADD_STAT(numOpsNotNOP, statistics::units::Count::get(),
|
|
"Number of Ops (including micro ops) Simulated"),
|
|
ADD_STAT(cpi, statistics::units::Rate<
|
|
statistics::units::Cycle, statistics::units::Count>::get(),
|
|
"CPI: cycles per instruction (thread level)"),
|
|
ADD_STAT(ipc, statistics::units::Rate<
|
|
statistics::units::Count, statistics::units::Cycle>::get(),
|
|
"IPC: instructions per cycle (thread level)"),
|
|
ADD_STAT(numMemRefs, statistics::units::Count::get(),
|
|
"Number of memory references committed"),
|
|
ADD_STAT(numFpInsts, statistics::units::Count::get(),
|
|
"Number of float instructions"),
|
|
ADD_STAT(numIntInsts, statistics::units::Count::get(),
|
|
"Number of integer instructions"),
|
|
ADD_STAT(numLoadInsts, statistics::units::Count::get(),
|
|
"Number of load instructions"),
|
|
ADD_STAT(numStoreInsts, statistics::units::Count::get(),
|
|
"Number of store instructions"),
|
|
ADD_STAT(numVecInsts, statistics::units::Count::get(),
|
|
"Number of vector instructions"),
|
|
ADD_STAT(committedInstType, statistics::units::Count::get(),
|
|
"Class of committed instruction."),
|
|
ADD_STAT(committedControl, statistics::units::Count::get(),
|
|
"Class of control type instructions committed")
|
|
{
|
|
numInsts
|
|
.prereq(numInsts);
|
|
|
|
cpi.precision(6);
|
|
ipc.precision(6);
|
|
|
|
committedInstType
|
|
.init(enums::Num_OpClass)
|
|
.flags(statistics::total | statistics::pdf | statistics::dist);
|
|
|
|
for (unsigned i = 0; i < Num_OpClasses; ++i) {
|
|
committedInstType.subname(i, enums::OpClassStrings[i]);
|
|
}
|
|
|
|
committedControl
|
|
.init(StaticInstFlags::Flags::Num_Flags)
|
|
.flags(statistics::nozero);
|
|
|
|
for (unsigned i = 0; i < StaticInstFlags::Flags::Num_Flags; i++) {
|
|
committedControl.subname(i, StaticInstFlags::FlagsStrings[i]);
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
BaseCPU::
|
|
CommitCPUStats::updateComCtrlStats(const StaticInstPtr staticInst)
|
|
{
|
|
/* Add a count for every control instruction type */
|
|
if (staticInst->isControl()) {
|
|
if (staticInst->isReturn()) {
|
|
committedControl[gem5::StaticInstFlags::Flags::IsReturn]++;
|
|
}
|
|
if (staticInst->isCall()) {
|
|
committedControl[gem5::StaticInstFlags::Flags::IsCall]++;
|
|
}
|
|
if (staticInst->isDirectCtrl()) {
|
|
committedControl[gem5::StaticInstFlags::Flags::IsDirectControl]++;
|
|
}
|
|
if (staticInst->isIndirectCtrl()) {
|
|
committedControl
|
|
[gem5::StaticInstFlags::Flags::IsIndirectControl]++;
|
|
}
|
|
if (staticInst->isCondCtrl()) {
|
|
committedControl[gem5::StaticInstFlags::Flags::IsCondControl]++;
|
|
}
|
|
if (staticInst->isUncondCtrl()) {
|
|
committedControl[gem5::StaticInstFlags::Flags::IsUncondControl]++;
|
|
}
|
|
committedControl[gem5::StaticInstFlags::Flags::IsControl]++;
|
|
}
|
|
}
|
|
|
|
} // namespace gem5
|