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2ee6e7ab5f3ea50080a9448e6bd8defcdb534640
gem5/arch
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Gabe Black 2ee6e7ab5f Added ev5.hh to files which should include it directly, now that it isn't included within isa_traits.hh
--HG--
extra : convert_revision : e49935da238a299e681f9137ad3c0b7dc0e226a3
2006-03-10 17:56:41 -05:00
..
alpha
Added ev5.hh to files which should include it directly, now that it isn't included within isa_traits.hh
2006-03-10 17:56:41 -05:00
mips
last changes before big merge
2006-03-09 03:27:51 -05:00
sparc
fix merging issues
2006-03-09 16:17:10 -05:00
isa_parser.py
Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included.
2006-03-03 15:28:25 -05:00
isa_specific.hh
Auto-generate arch/foo.hh "switch headers" in scons.
2006-02-22 22:22:06 -05:00
SConscript
Pushed ev5.hh out of the non-alpha code.
2006-03-07 14:08:01 -05:00
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