Giacomo Travaglini 2dd1842a67 arch-arm: Fix short descriptors cacheability during table walks ...

This implies checking for the SCTLR.C bit TTBR1.IRGN0 bits.

Change-Id: I341faf85692ce2d2b4afd30a2f4aabac0e133192
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22724
Tested-by: kokoro <noreply+kokoro@google.com>

2019-11-18 09:45:55 +00:00

..

arch

arch-arm: Fix short descriptors cacheability during table walks

2019-11-18 09:45:55 +00:00

base

tests, base: Removed ambiguity from base/intmath.hh

2019-11-14 08:31:52 +00:00

cpu

cpu: Fix a bug in getCurrentInstCount in the checker CPU.

2019-11-07 11:03:46 +00:00

dev

arch-arm: Refactor code to check if gic is GicV2

2019-11-14 00:04:20 +00:00

doc

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

gpu-compute: Fix overriden errors

2019-09-20 22:42:31 +00:00

kern

kern: When dumping dmesg, detect the byte order dynamically.

2019-10-30 22:29:23 +00:00

learning_gem5

mem-ruby: Allow Ruby to use all replacement policies in Classic

2019-10-11 03:29:29 +00:00

mem

mem-ruby: Reset Ruby Sequencer Outstanding Requests stats

2019-11-05 12:28:24 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

misc: Added line wrapping functionality for Sim-Object desc

2019-09-30 19:50:26 +00:00

sim

tests: Added GTests for byteswap.hh

2019-11-16 07:25:58 +00:00

systemc

systemc: Remove boost dependency caused by tlm

2019-11-07 05:01:20 +00:00

unittest

tests: Added GTests for base/str.cc

2019-10-24 16:25:09 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: Move the marshal binary to the build directory

2019-05-21 15:46:50 +00:00