3a7192d682
hasBeenPrefetched can now take a requestor id and returns true only if the block was prefetched by a prefetcher with the same id. This may be necessary to properly train multiple prefetchers attached to the same cache. If returns true if the block was prefetched by any prefetcher when the id is not provided. Related JIRA: https://gem5.atlassian.net/browse/GEM5-457 https://gem5.atlassian.net/browse/GEM5-1112 Change-Id: I205e000fd5ff100e5a5d24d88bca7c6a46689ab2 Signed-off-by: Tiago Mück <tiago.muck@arm.com>
126 lines
4.7 KiB
C++
126 lines
4.7 KiB
C++
/*
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* Copyright (c) 2023 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_CACHE_PROBE_ARG_HH__
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#define __MEM_CACHE_PROBE_ARG_HH__
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#include "mem/packet.hh"
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namespace gem5
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{
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/**
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* Provides generic cache lookup functions. A cache may provide
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* a CacheAccessor object to other components that need to perform
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* a lookup outside the normal cache control flow. Currently this
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* is used by prefetchers that perform lookups when notified by
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* cache events.
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*/
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struct CacheAccessor
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{
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/** Determine if address is in cache */
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virtual bool inCache(Addr addr, bool is_secure) const = 0;
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/** Determine if address has been prefetched */
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virtual bool hasBeenPrefetched(Addr addr, bool is_secure) const = 0;
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/** Determine if address has been prefetched by the requestor */
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virtual bool hasBeenPrefetched(Addr addr, bool is_secure,
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RequestorID requestor) const = 0;
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/** Determine if address is in cache miss queue */
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virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
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/** Determine if cache is coalescing writes */
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virtual bool coalesce() const = 0;
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};
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/**
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* Information provided to probes on a cache event.
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* @sa ppHit, ppMiss, ppFill in gem5::BaseCache (src/mem/cache/base.hh)
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*/
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class CacheAccessProbeArg
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{
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public:
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/** Packet that triggered the cache access*/
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PacketPtr pkt;
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/** Accessor for the cache */
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CacheAccessor &cache;
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CacheAccessProbeArg(PacketPtr _pkt, CacheAccessor &_cache)
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:pkt(_pkt), cache(_cache)
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{
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}
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};
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/**
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* A data contents update is composed of the updated block's address,
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* the old contents, and the new contents.
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* @sa ppDataUpdate in gem5::BaseCache (src/mem/cache/base.hh)
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*/
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struct CacheDataUpdateProbeArg
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{
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/** The updated block's address. */
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Addr addr;
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/** Whether the block belongs to the secure address space. */
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bool isSecure;
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/** Block original requestor */
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const RequestorID requestorID;
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/** The stale data contents. If zero-sized this update is a fill. */
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std::vector<uint64_t> oldData;
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/** The new data contents. If zero-sized this is an invalidation. */
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std::vector<uint64_t> newData;
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/** Set if the update is from a prefetch or evicting a prefetched
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* block that was never used. */
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bool hwPrefetched;
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/** Accessor for the cache */
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CacheAccessor &accessor;
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CacheDataUpdateProbeArg(Addr _addr, bool is_secure,
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RequestorID _requestorID,
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CacheAccessor &_accessor)
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: addr(_addr), isSecure(is_secure), requestorID(_requestorID),
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oldData(), newData(), accessor(_accessor)
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{
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}
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};
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} // namespace gem5
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#endif //__MEM_CACHE_PROBE_ARG_HH__
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