278 lines
8.8 KiB
C++
278 lines
8.8 KiB
C++
/*
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* Copyright (c) 2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Matt Evans
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*/
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/** @file
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* Implementiation of a GIC-400 List Register-based VGIC interface.
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* The VGIC is, in this implementation, completely separate from the GIC itself.
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* Only a VIRQ line to the CPU and a PPI line to the GIC (for a HV maintenance IRQ)
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* is required.
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*
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* The mode in which the List Registers may flag (via LR.HW) that a hardware EOI
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* is to be performed is NOT supported. (This requires tighter integration with
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* the GIC.)
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*/
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#ifndef __DEV_ARM_VGIC_H__
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#define __DEV_ARM_VGIC_H__
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#include <algorithm>
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#include <array>
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#include "base/addr_range.hh"
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#include "base/bitunion.hh"
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#include "cpu/intr_control.hh"
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#include "dev/io_device.hh"
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#include "dev/platform.hh"
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#include "params/VGic.hh"
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class VGic : public PioDevice
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{
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private:
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static const int VGIC_CPU_MAX = 256;
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static const int NUM_LR = 4;
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static const int GICH_SIZE = 0x200;
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static const int GICH_REG_SIZE = 0x2000;
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static const int GICH_HCR = 0x000;
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static const int GICH_VTR = 0x004;
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static const int GICH_VMCR = 0x008;
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static const int GICH_MISR = 0x010;
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static const int GICH_EISR0 = 0x020;
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static const int GICH_EISR1 = 0x024;
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static const int GICH_ELSR0 = 0x030;
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static const int GICH_ELSR1 = 0x034;
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static const int GICH_APR0 = 0x0f0;
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static const int GICH_LR0 = 0x100;
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static const int GICH_LR1 = 0x104;
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static const int GICH_LR2 = 0x108;
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static const int GICH_LR3 = 0x10c;
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static const int GICV_SIZE = 0x2000;
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static const int GICV_CTLR = 0x000;
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static const int GICV_PMR = 0x004;
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static const int GICV_BPR = 0x008;
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static const int GICV_IAR = 0x00c;
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static const int GICV_EOIR = 0x010;
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static const int GICV_RPR = 0x014;
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static const int GICV_HPPIR = 0x018;
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static const int GICV_ABPR = 0x01c;
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static const int GICV_AIAR = 0x020;
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static const int GICV_AEOIR = 0x024;
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static const int GICV_AHPPIR = 0x028;
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static const int GICV_APR0 = 0x0d0;
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static const int GICV_IIDR = 0x0fc;
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static const int GICV_DIR = 0x1000;
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static const uint32_t LR_PENDING = 1;
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static const uint32_t LR_ACTIVE = 2;
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/** Event definition to post interrupt to CPU after a delay
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*/
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class PostVIntEvent : public Event
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{
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private:
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uint32_t cpu;
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Platform *platform;
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public:
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PostVIntEvent( uint32_t c, Platform* p)
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: cpu(c), platform(p)
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{ }
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void process() { platform->intrctrl->post(cpu, ArmISA::INT_VIRT_IRQ, 0);}
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const char *description() const { return "Post VInterrupt to CPU"; }
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};
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PostVIntEvent *postVIntEvent[VGIC_CPU_MAX];
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bool maintIntPosted[VGIC_CPU_MAX];
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bool vIntPosted[VGIC_CPU_MAX];
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Platform *platform;
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BaseGic *gic;
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Addr vcpuAddr;
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Addr hvAddr;
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Tick pioDelay;
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int maintInt;
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BitUnion32(ListReg)
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Bitfield<31> HW;
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Bitfield<30> Grp1;
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Bitfield<29,28> State;
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Bitfield<27,23> Priority;
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Bitfield<19> EOI;
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Bitfield<12,10> CpuID;
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Bitfield<9,0> VirtualID;
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EndBitUnion(ListReg)
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BitUnion32(HCR)
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Bitfield<31,27> EOICount;
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Bitfield<7> VGrp1DIE;
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Bitfield<6> VGrp1EIE;
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Bitfield<5> VGrp0DIE;
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Bitfield<4> VGrp0EIE;
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Bitfield<3> NPIE;
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Bitfield<2> LRENPIE;
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Bitfield<1> UIE;
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Bitfield<0> En;
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EndBitUnion(HCR)
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BitUnion32(VCTLR)
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Bitfield<9> EOImode;
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Bitfield<4> CPBR;
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Bitfield<3> FIQEn;
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Bitfield<2> AckCtl;
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Bitfield<1> EnGrp1;
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Bitfield<0> En; // This gets written to enable, not group 1.
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EndBitUnion(VCTLR)
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/* State per CPU. EVERYTHING should be in this struct and simply replicated
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* N times.
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*/
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struct vcpuIntData : public Serializable {
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vcpuIntData()
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: vctrl(0), hcr(0), eisr(0), VMGrp0En(0), VMGrp1En(0),
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VMAckCtl(0), VMFiqEn(0), VMCBPR(0), VEM(0), VMABP(0), VMBP(0),
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VMPriMask(0)
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{
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std::fill(LR.begin(), LR.end(), 0);
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}
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virtual ~vcpuIntData() {}
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std::array<ListReg, NUM_LR> LR;
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VCTLR vctrl;
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HCR hcr;
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uint64_t eisr;
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/* Host info, guest info (should be 100% accessible via GICH_* regs!) */
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uint8_t VMGrp0En;
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uint8_t VMGrp1En;
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uint8_t VMAckCtl;
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uint8_t VMFiqEn;
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uint8_t VMCBPR;
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uint8_t VEM;
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uint8_t VMABP;
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uint8_t VMBP;
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uint8_t VMPriMask;
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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};
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struct std::array<vcpuIntData, VGIC_CPU_MAX> vcpuData;
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public:
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typedef VGicParams Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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VGic(const Params *p);
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AddrRangeList getAddrRanges() const override;
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Tick read(PacketPtr pkt) override;
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Tick write(PacketPtr pkt) override;
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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private:
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Tick readVCpu(PacketPtr pkt);
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Tick readCtrl(PacketPtr pkt);
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Tick writeVCpu(PacketPtr pkt);
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Tick writeCtrl(PacketPtr pkt);
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void updateIntState(ContextID ctx_id);
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uint32_t getMISR(struct vcpuIntData *vid);
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void postVInt(uint32_t cpu, Tick when);
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void unPostVInt(uint32_t cpu);
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void postMaintInt(uint32_t cpu);
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void unPostMaintInt(uint32_t cpu);
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unsigned int lrPending(struct vcpuIntData *vid)
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{
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unsigned int pend = 0;
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for (int i = 0; i < NUM_LR; i++) {
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if (vid->LR[i].State & LR_PENDING)
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pend++;
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}
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return pend;
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}
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unsigned int lrValid(struct vcpuIntData *vid)
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{
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unsigned int valid = 0;
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for (int i = 0; i < NUM_LR; i++) {
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if (vid->LR[i].State)
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valid++;
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}
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return valid;
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}
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/** Returns LR index or -1 if none pending */
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int findHighestPendingLR(struct vcpuIntData *vid)
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{
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unsigned int prio = 0xff;
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int p = -1;
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for (int i = 0; i < NUM_LR; i++) {
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if ((vid->LR[i].State & LR_PENDING) && (vid->LR[i].Priority < prio)) {
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p = i;
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prio = vid->LR[i].Priority;
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}
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}
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return p;
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}
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int findLRForVIRQ(struct vcpuIntData *vid, int virq, int vcpu)
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{
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for (int i = 0; i < NUM_LR; i++) {
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if (vid->LR[i].State &&
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vid->LR[i].VirtualID == virq &&
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vid->LR[i].CpuID == vcpu)
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return i;
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}
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return -1;
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}
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};
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#endif
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