Min Kyu Jeong 745df74fe0 O3: prevent a squash when completeAcc() modifies misc reg through TC. ...

This happens on ARM instructions when they update the IT state bits.
Code and associated comment was copied from execute() and initiateAcc() methods

2010-11-15 14:04:04 -06:00

..

arch

ARM: Return an FailUnimp instruction when an unimplemented CP15 register is accessed.

2010-11-15 14:04:04 -06:00

base

sim: Use forward declarations for ports.

2010-11-08 13:58:22 -06:00

cpu

O3: prevent a squash when completeAcc() modifies misc reg through TC.

2010-11-15 14:04:04 -06:00

dev

ARM: Add a Keyboard Mouse Interface controller

2010-11-15 14:04:03 -06:00

doxygen

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kern

ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.

2010-10-31 00:07:20 -07:00

mem

ARM: Add checkpointing support

2010-11-08 13:58:25 -06:00

python

Params: Fix an off by one error and a misleading comment.

2010-11-11 11:58:09 -08:00

sim

ARM: Add checkpointing support

2010-11-08 13:58:25 -06:00

unittest

stats: cleanup a few small problems in stats

2010-07-21 15:53:53 -07:00

Doxyfile

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SConscript

SCons: Cleanup SCons output during compile

2010-11-15 14:04:04 -06:00