Applies the `pyupgrade` hook to all files in the repo. Change-Id: I9879c634a65c5fcaa9567c63bc5977ff97d5d3bf
81 lines
3.1 KiB
Python
81 lines
3.1 KiB
Python
# Copyright (c) 2015 Jason Power
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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""" This file creates a system with Ruby caches and runs the ruby random tester
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See Part 3 in the Learning gem5 book:
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http://gem5.org/documentation/learning_gem5/part3/MSIintro
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IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
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also needs to be updated. For now, email Jason <jason@lowepower.com>
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"""
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# import the m5 (gem5) library created when gem5 is built
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import m5
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# import all of the SimObjects
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from m5.objects import *
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from test_caches import TestCacheSystem
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# create the system we are going to simulate
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system = System()
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# Set the clock frequency of the system (and all of its children)
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system.clk_domain = SrcClockDomain()
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system.clk_domain.clock = "1GHz"
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system.clk_domain.voltage_domain = VoltageDomain()
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# Set up the system
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system.mem_mode = "timing" # Use timing accesses
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system.mem_ranges = [AddrRange("512MB")] # Create an address range
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# Create the tester
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system.tester = RubyTester(
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checks_to_complete=100, wakeup_frequency=10, num_cpus=2
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)
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# Create a simple memory controller and connect it to the membus
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system.mem_ctrl = SimpleMemory(latency="50ns", bandwidth="0GB/s")
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system.mem_ctrl.range = system.mem_ranges[0]
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# Create the Ruby System
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system.caches = TestCacheSystem()
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system.caches.setup(system, system.tester, [system.mem_ctrl])
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# set up the root SimObject and start the simulation
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root = Root(full_system=False, system=system)
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency("1ns")
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# instantiate all of the objects we've created above
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m5.instantiate()
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print("Beginning simulation!")
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exit_event = m5.simulate()
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print(f"Exiting @ tick {m5.curTick()} because {exit_event.getCause()}")
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