281afe2be0
arch/arm/isa_traits.hh no longer has using namespace ArmISA, and also no longer directly or indirectly provides interrupt number related constants. Change-Id: Ieda31d1db4f85632a555b2f72ee8bff0aa159eee Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35037 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
115 lines
3.8 KiB
C++
115 lines
3.8 KiB
C++
/*
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* Copyright 2019 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/arm/fastmodel/iris/interrupts.hh"
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#include "arch/arm/fastmodel/iris/thread_context.hh"
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#include "arch/arm/interrupts.hh"
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#include "arch/arm/miscregs.hh"
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#include "arch/arm/miscregs_types.hh"
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#include "arch/arm/types.hh"
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#include "params/IrisInterrupts.hh"
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void
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Iris::Interrupts::serialize(CheckpointOut &cp) const
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{
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using namespace ArmISA;
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CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
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CPSR orig_cpsr = cpsr;
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SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
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SCR orig_scr = scr;
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HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
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HCR orig_hcr = hcr;
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// Set up state so we can get either physical or virtual interrupt bits.
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cpsr.mode = 0;
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cpsr.width = 0;
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cpsr.el = EL1;
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tc->setMiscReg(MISCREG_CPSR, cpsr);
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scr.eel2 = 1;
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tc->setMiscReg(MISCREG_SCR, scr);
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// Get the virtual bits.
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hcr.imo = 1;
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hcr.fmo = 1;
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hcr.amo = 1;
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tc->setMiscReg(MISCREG_HCR_EL2, hcr);
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RegVal isr_el1 = tc->readMiscRegNoEffect(MISCREG_ISR_EL1);
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// There is also a virtual abort, but it's not used by gem5.
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bool virt_irq = bits(7, isr_el1);
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bool virt_fiq = bits(6, isr_el1);
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// Get the physical bits.
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hcr.imo = 0;
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hcr.fmo = 0;
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hcr.amo = 0;
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tc->setMiscReg(MISCREG_HCR_EL2, hcr);
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isr_el1 = tc->readMiscRegNoEffect(MISCREG_ISR_EL1);
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bool phys_abort = bits(8, isr_el1);
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bool phys_irq = bits(7, isr_el1);
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bool phys_fiq = bits(6, isr_el1);
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tc->setMiscReg(MISCREG_CPSR, orig_cpsr);
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tc->setMiscReg(MISCREG_SCR_EL3, orig_scr);
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tc->setMiscReg(MISCREG_HCR_EL2, orig_hcr);
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bool interrupts[ArmISA::NumInterruptTypes];
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uint64_t intStatus = 0;
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for (bool &i: interrupts)
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i = false;
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interrupts[ArmISA::INT_ABT] = phys_abort;
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interrupts[ArmISA::INT_IRQ] = phys_irq;
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interrupts[ArmISA::INT_FIQ] = phys_fiq;
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interrupts[ArmISA::INT_SEV] = tc->readMiscReg(MISCREG_SEV_MAILBOX);
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interrupts[ArmISA::INT_VIRT_IRQ] = virt_irq;
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interrupts[ArmISA::INT_VIRT_FIQ] = virt_fiq;
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for (int i = 0; i < NumInterruptTypes; i++) {
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if (interrupts[i])
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intStatus |= (0x1ULL << i);
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}
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SERIALIZE_ARRAY(interrupts, NumInterruptTypes);
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SERIALIZE_SCALAR(intStatus);
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}
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void
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Iris::Interrupts::unserialize(CheckpointIn &cp)
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{
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}
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Iris::Interrupts *
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IrisInterruptsParams::create()
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{
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return new Iris::Interrupts(this);
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}
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