cd772c1951
Change-Id: Ia31919ef19f973aa7af973889366412f3999342a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52042 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Gabe Black <gabe.black@gmail.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
82 lines
2.7 KiB
C++
82 lines
2.7 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_INTELTRACE_HH__
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#define __CPU_INTELTRACE_HH__
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "debug/ExecEnable.hh"
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#include "params/IntelTrace.hh"
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#include "sim/insttracer.hh"
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namespace gem5
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{
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namespace Trace {
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class IntelTraceRecord : public InstRecord
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{
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public:
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IntelTraceRecord(Tick _when, ThreadContext *_thread,
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const StaticInstPtr _staticInst, const PCStateBase &_pc,
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const StaticInstPtr _macroStaticInst = NULL)
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: InstRecord(_when, _thread, _staticInst, _pc,
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_macroStaticInst)
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{
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}
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void dump();
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};
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class IntelTrace : public InstTracer
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{
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public:
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IntelTrace(const IntelTraceParams &p) : InstTracer(p)
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{}
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IntelTraceRecord *
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getInstRecord(Tick when, ThreadContext *tc,
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const StaticInstPtr staticInst, const PCStateBase &pc,
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const StaticInstPtr macroStaticInst = NULL)
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{
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if (!debug::ExecEnable)
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return NULL;
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return new IntelTraceRecord(when, tc, staticInst, pc, macroStaticInst);
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}
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};
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} // namespace Trace
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} // namespace gem5
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#endif // __CPU_INTELTRACE_HH__
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