* stdlib,configs,tests: Remove `Resource` class use This class is deprecated, but was still used in various example configuration scriots and tests. This patch replaces it with the `obtain_resource` function. Change-Id: I0c89bf17783ccaaafc18072aaeefb5d1e207bc55 * configs: Remove `CustomDiskImageResource` use The class is deprecated but was still used in the SPEC example scripts. This patch replaces it with the `DiskImageResource` class. Change-Id: Ie0697fe59a3d737b05eb45ff3bc964f42b0387e0 * configs,tests: Remove `CustomResource` use This class is deprecated but was still used in example scripts and mentioned, incorrectly, in comments in the pyunit tests. This patch removes these. Change-Id: Icb6d02f47a5b72cd58551e5dcd59cc72d6a91a01 * stdlib: Remove '\' in Workload docstring example This example shows how to use the Workload. The backslash is not correct Python and would fail if used in this way. Co-authored-by: Jason Lowe-Power <jason@lowepower.com> --------- Co-authored-by: Jason Lowe-Power <jason@lowepower.com>
107 lines
4.2 KiB
Python
107 lines
4.2 KiB
Python
# Copyright (c) 2022 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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"""
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This gem5 configuation script creates a simple board sharing the same
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structure as the one in
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configs/example/gem5_library/checkpoint/riscv-hello-save-checkpoint.py.
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This script restores the checkpoint generated by the above script, and
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runs the rest of "riscv-hello" binary simulation.
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This configuration serves as an example of restoring a checkpoint.
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This is setup is the close to the simplest setup possible using the gem5
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library. It does not contain any kind of caching, IO, or any non-essential
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components.
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Usage
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-----
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```
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scons build/RISCV/gem5.opt
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./build/RISCV/gem5.opt \
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configs/example/gem5_library/checkpoint/riscv-hello-restore-checkpoint.py
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```
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"""
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from gem5.isas import ISA
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from gem5.utils.requires import requires
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from gem5.resources.resource import obtain_resource
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from gem5.components.memory import SingleChannelDDR3_1600
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from gem5.components.processors.cpu_types import CPUTypes
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from gem5.components.boards.simple_board import SimpleBoard
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from gem5.components.cachehierarchies.classic.no_cache import NoCache
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from gem5.components.processors.simple_processor import SimpleProcessor
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from gem5.simulate.simulator import Simulator
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# This check ensures the gem5 binary is compiled to the RISCV ISA target.
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# If not, an exception will be thrown.
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requires(isa_required=ISA.RISCV)
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# In this setup we don't have a cache. `NoCache` can be used for such setups.
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cache_hierarchy = NoCache()
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# We use a single channel DDR3_1600 memory system
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memory = SingleChannelDDR3_1600(size="32MB")
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# We use a simple Timing processor with one core.
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processor = SimpleProcessor(
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cpu_type=CPUTypes.TIMING, isa=ISA.RISCV, num_cores=1
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)
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# The gem5 library simble board which can be used to run simple SE-mode
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# simulations.
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board = SimpleBoard(
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clk_freq="3GHz",
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
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)
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# Here we set the workload. In this case we want to run a simple "Hello World!"
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# program compiled to the RISCV ISA. The `Resource` class will automatically
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# download the binary from the gem5 Resources cloud bucket if it's not already
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# present.
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# We get the pre-taken checkpoint from gem5-resources. This checkpoint
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# was taken from running this gem5 configuration script,
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# configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
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board.set_se_binary_workload(
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# the workload should be the same as the save-checkpoint script
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obtain_resource("riscv-hello"),
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checkpoint=obtain_resource("riscv-hello-example-checkpoint-v23"),
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)
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simulator = Simulator(
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board=board,
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full_system=False,
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)
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simulator.run()
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print(
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"Exiting @ tick {} because {}.".format(
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simulator.get_current_tick(), simulator.get_last_exit_event_cause()
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)
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)
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