Ali Saidi 271b9a5435 first cut at a sparc tlb ...

src/arch/sparc/SConscript:
    Add code to serialize/unserialze tlb entries
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    update asi names for how they're listed in the supplement
    add asis
    add more asi functions
src/arch/sparc/isa_traits.hh:
    move the interrupt stuff and some basic address space stuff into isa traits
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    add mmu registers to tlb
    get rid of implicit asi stuff... the tlb will handle it
src/arch/sparc/regfile.hh:
    make isnt/dataAsid return ints not asis
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
    first cut at sparc tlb
src/arch/sparc/vtophys.hh:
    pagatable nedes to be included here
src/mem/request.hh:
    add asi and if the request is a memory mapped register to the requset object
src/sim/host.hh:
    fix incorrect definition of LL

--HG--
extra : convert_revision : 6c85cd1681c62c8cd8eab04f70b1f15a034b0aa3

2006-11-23 01:42:57 -05:00

..

cache

Handle packets being deleted by lower level properly.

2006-11-12 09:06:15 -05:00

config

Backing in more changsets, getting closer to compile

2006-06-28 14:35:00 -04:00

bridge.cc

Use PacketPtr everywhere

2006-10-20 00:10:12 -07:00

bridge.hh

Use PacketPtr everywhere

2006-10-20 00:10:12 -07:00

bus.cc

Be sure to populate the packet's finishTime field in the atomic timing case.

2006-11-09 11:37:26 -05:00

bus.hh

Fix up bus draining and add draining to the caches.

2006-11-07 14:25:54 -05:00

dram.cc

Use PacketPtr everywhere

2006-10-20 00:10:12 -07:00

dram.hh

Use PacketPtr everywhere

2006-10-20 00:10:12 -07:00

mem_object.cc

Updated Authors from bk prs info

2006-05-31 19:26:56 -04:00

mem_object.hh

Fix up doxygen.

2006-08-14 19:25:07 -04:00

packet_access.hh

refactor code for the packet, get rid of packet_impl.hh

2006-10-19 23:38:45 -07:00

packet.cc

Fix functional access errors related to delayed respnoses in cachePort

2006-11-12 06:35:39 -05:00

packet.hh

Fix functional access errors related to delayed respnoses in cachePort

2006-11-12 06:35:39 -05:00

page_table.cc

initialize end, clean up loop

2006-10-19 23:35:59 -07:00

page_table.hh

add code to serialize se structures. Lisa is working on the python side of things and will test

2006-10-17 19:38:36 -04:00

physical.cc

Physical memory overrides the tport version of recvFunctional, need to do the

2006-11-12 09:30:12 -05:00

physical.hh

Use PacketPtr everywhere

2006-10-20 00:10:12 -07:00

port_impl.hh

Put the ProcessInfo and StackTrace objects into the ISA namespaces.

2006-11-08 00:52:04 -05:00

port.cc

refactor code for the packet, get rid of packet_impl.hh

2006-10-19 23:38:45 -07:00

port.hh

Ports now have a pointer to the MemObject that owns it (can be NULL).

2006-10-31 13:59:30 -05:00

request.hh

first cut at a sparc tlb

2006-11-23 01:42:57 -05:00

tport.cc

Don't insert reponses into the list more than once

2006-11-12 07:16:34 -05:00

tport.hh

Merge ktlim@zizzer:/bk/newmem

2006-10-31 14:37:19 -05:00

translating_port.cc

Updated Authors from bk prs info

2006-05-31 19:26:56 -04:00

translating_port.hh

Updated Authors from bk prs info

2006-05-31 19:26:56 -04:00

vport.cc

Fix up doxygen.

2006-08-14 19:25:07 -04:00

vport.hh

Fix up doxygen.

2006-08-14 19:25:07 -04:00