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25bb18f12b7983e46e5b0544de18445d3b60d41a
gem5/src/mem
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Nilay Vaish 25bb18f12b ruby: network: garnet: remove functions for computing power
2014-10-11 15:02:23 -05:00
..
cache
mem: Add packet sanity checks to cache and MSHRs
2014-10-09 17:51:56 -04:00
protocol
ruby: mesi: slight renaming
2014-10-11 15:02:23 -05:00
ruby
ruby: network: garnet: remove functions for computing power
2014-10-11 15:02:23 -05:00
slicc
ruby: message buffers: significant changes
2014-09-01 16:55:47 -05:00
abstract_mem.cc
mem: Wakeup sleeping CPUs without caches on LLSC
2014-03-07 15:56:23 -05:00
abstract_mem.hh
mem: Avoid explicitly zeroing the memory backing store
2013-05-30 12:53:54 -04:00
AbstractMemory.py
mem: Change AbstractMemory defaults to match the common case
2013-08-19 03:52:33 -04:00
addr_mapper.cc
mem: Set the cache line size on a system level
2013-07-18 08:31:16 -04:00
addr_mapper.hh
mem: Set the cache line size on a system level
2013-07-18 08:31:16 -04:00
AddrMapper.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
bridge.cc
mem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 17:18:32 -04:00
bridge.hh
mem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 17:18:32 -04:00
Bridge.py
mem: Tidy up the bridge with const and additional checks
2013-06-27 05:49:49 -04:00
coherent_xbar.cc
mem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 17:18:32 -04:00
coherent_xbar.hh
mem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 17:18:32 -04:00
comm_monitor.cc
misc: Fix a bunch of minor issues identified by static analysis
2014-09-27 09:08:29 -04:00
comm_monitor.hh
misc: Fix a bunch of minor issues identified by static analysis
2014-09-27 09:08:29 -04:00
CommMonitor.py
mem: Auto-generate CommMonitor trace file names
2014-05-09 18:58:46 -04:00
dram_ctrl.cc
mem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 17:18:32 -04:00
dram_ctrl.hh
mem: DRAMPower integration for on-line DRAM power stats
2014-07-29 17:22:44 +01:00
DRAMCtrl.py
mem: Remove DRAMSim2 DDR3 configuration
2014-10-09 17:52:04 -04:00
drampower.cc
mem: Add DRAMPower wrapping class
2014-07-29 17:29:36 +01:00
drampower.hh
mem: Add DRAMPower wrapping class
2014-07-29 17:29:36 +01:00
dramsim2_wrapper.cc
mem: Add a wrapped DRAMSim2 memory controller
2014-02-18 05:50:53 -05:00
dramsim2_wrapper.hh
mem: Add a wrapped DRAMSim2 memory controller
2014-02-18 05:50:53 -05:00
dramsim2.cc
mem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 17:18:32 -04:00
dramsim2.hh
mem: Fix DRAMSim2 cycle check when restoring from checkpoint
2014-08-26 10:14:38 -04:00
DRAMSim2.py
mem: Add a wrapped DRAMSim2 memory controller
2014-02-18 05:50:53 -05:00
fs_translating_port_proxy.cc
arch: Resurrect the NOISA build target and rename it NULL
2013-09-04 13:22:57 -04:00
fs_translating_port_proxy.hh
arch: Resurrect the NOISA build target and rename it NULL
2013-09-04 13:22:57 -04:00
mem_object.cc
Port: Add protocol-agnostic ports in the port hierarchy
2012-10-15 08:12:35 -04:00
mem_object.hh
Port: Add protocol-agnostic ports in the port hierarchy
2012-10-15 08:12:35 -04:00
MemObject.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
mport.cc
MEM: Separate snoops and normal memory requests/responses
2012-04-14 05:45:07 -04:00
mport.hh
MEM: Separate requests and responses for timing accesses
2012-05-01 13:40:42 -04:00
multi_level_page_table_impl.hh
arch: Cleanup unused ISA traits constants
2014-09-03 07:42:21 -04:00
multi_level_page_table.cc
mem: adding a multi-level page table class
2014-04-01 12:18:12 -05:00
multi_level_page_table.hh
mem: adding a multi-level page table class
2014-04-01 12:18:12 -05:00
noncoherent_xbar.cc
mem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 17:18:32 -04:00
noncoherent_xbar.hh
mem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 17:18:32 -04:00
packet_access.hh
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
2009-09-23 08:34:21 -07:00
packet_queue.cc
mem: Allow packet queue to move next send event forward
2014-10-09 17:51:52 -04:00
packet_queue.hh
mem: Packet queue clean up
2014-09-03 07:42:28 -04:00
packet.cc
misc: Use safe_cast when assumptions are made about return value
2014-09-19 10:35:11 -04:00
packet.hh
misc: Fix a bunch of minor issues identified by static analysis
2014-09-27 09:08:29 -04:00
page_table.cc
mem: adding a multi-level page table class
2014-04-01 12:18:12 -05:00
page_table.hh
arch: Cleanup unused ISA traits constants
2014-09-03 07:42:21 -04:00
physical.cc
misc: Fix a bunch of minor issues identified by static analysis
2014-09-27 09:08:29 -04:00
physical.hh
mem: Merge ranges that are part of the conf table
2013-01-07 13:05:38 -05:00
port_proxy.cc
mem: Set the cache line size on a system level
2013-07-18 08:31:16 -04:00
port_proxy.hh
arch: Resurrect the NOISA build target and rename it NULL
2013-09-04 13:22:57 -04:00
port.cc
mem: Set the cache line size on a system level
2013-07-18 08:31:16 -04:00
port.hh
mem: Provide better diagnostic for unconnected port
2014-09-27 09:08:30 -04:00
qport.hh
ruby: Simplify RubyPort flow control and routing
2014-02-23 19:16:16 -06:00
request.hh
mem: Add accessor function for vaddr
2014-09-09 04:36:33 -04:00
SConscript
mem: Add DRAMPower wrapping class
2014-07-29 17:29:36 +01:00
se_translating_port_proxy.cc
arch: Cleanup unused ISA traits constants
2014-09-03 07:42:21 -04:00
se_translating_port_proxy.hh
mem: adding a multi-level page table class
2014-04-01 12:18:12 -05:00
simple_mem.cc
mem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 17:18:32 -04:00
simple_mem.hh
mem: Add an internal packet queue in SimpleMemory
2013-08-19 03:52:25 -04:00
SimpleMemory.py
mem: Add an internal packet queue in SimpleMemory
2013-08-19 03:52:25 -04:00
snoop_filter.cc
mem: Add access statistics for the snoop filter
2014-04-25 12:36:16 +01:00
snoop_filter.hh
mem: Add access statistics for the snoop filter
2014-04-25 12:36:16 +01:00
tport.cc
mem: Replace check with panic where inhibited should not happen
2013-04-22 13:20:33 -04:00
tport.hh
Port: Hide the queue implementation in SimpleTimingPort
2012-07-09 12:35:42 -04:00
xbar.cc
mem: Output precise range when XBar has conflicts
2014-09-27 09:08:32 -04:00
xbar.hh
mem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 17:18:32 -04:00
XBar.py
mem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 17:18:32 -04:00