24504c9a3e
Invalidate requests align to system cache line size. This causes problems if the GPU cache hierarchy's cache line size is different than the system as the unlaigned requests never return, leading to deadlock on deferred dispatch. This commit uses the cache line size from the GPU memory manager and makes the cache line size there non-optional. Tested with multiple RubySystems where CPU side was 64B and GPU side was 128B cache lines.
371 lines
13 KiB
Python
371 lines
13 KiB
Python
# Copyright (c) 2021 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from this
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# software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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from common import (
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GPUTLBConfig,
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Simulation,
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)
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from common.Benchmarks import *
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from common.FSConfig import *
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from example.gpufs.Disjoint_VIPER import *
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from ruby import Ruby
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from system.amdgpu import *
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from m5.util import panic
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def makeGpuFSSystem(args):
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# Boot options are standard gem5 options plus:
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# - Framebuffer device emulation 0 to reduce driver code paths.
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# - Blacklist amdgpu as it cannot (currently) load in KVM CPU.
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# - Blacklist psmouse as amdgpu driver adds proprietary commands that
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# cause gem5 to panic.
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boot_options = [
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"earlyprintk=ttyS0",
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"console=ttyS0,9600",
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"lpj=7999923",
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f"root={args.root_partition}",
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"drm_kms_helper.fbdev_emulation=0",
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"modprobe.blacklist=amdgpu",
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"modprobe.blacklist=psmouse",
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]
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cmdline = " ".join(boot_options)
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if MemorySize(args.mem_size) < MemorySize("2GiB"):
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panic("Need at least 2GiB of system memory to load amdgpu module")
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# Use the common FSConfig to setup a Linux X86 System
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(TestCPUClass, test_mem_mode) = Simulation.getCPUClass(args.cpu_type)
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if test_mem_mode == "atomic":
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test_mem_mode = "atomic_noncaching"
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disks = [args.disk_image]
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if args.second_disk is not None:
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disks.extend([args.second_disk])
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bm = SysConfig(disks=disks, mem=args.mem_size)
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system = makeLinuxX86System(
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test_mem_mode, args.num_cpus, bm, True, cmdline=cmdline
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)
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system.workload.object_file = binary(args.kernel)
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# Set the cache line size for the entire system.
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system.cache_line_size = args.cacheline_size
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# Create a top-level voltage and clock domain.
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system.voltage_domain = VoltageDomain(voltage=args.sys_voltage)
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system.clk_domain = SrcClockDomain(
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clock=args.sys_clock, voltage_domain=system.voltage_domain
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)
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# Create a CPU voltage and clock domain.
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system.cpu_voltage_domain = VoltageDomain()
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system.cpu_clk_domain = SrcClockDomain(
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clock=args.cpu_clock, voltage_domain=system.cpu_voltage_domain
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)
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# Setup VGA ROM region
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system.shadow_rom_ranges = [AddrRange(0xC0000, size=Addr("128KiB"))]
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# Create specified number of CPUs. GPUFS really only needs one.
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system.cpu = [
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TestCPUClass(clk_domain=system.cpu_clk_domain, cpu_id=i)
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for i in range(args.num_cpus)
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]
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if ObjectList.is_kvm_cpu(TestCPUClass):
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system.kvm_vm = KvmVM()
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# Create AMDGPU and attach to southbridge
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shader = createGPU(system, args)
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connectGPU(system, args)
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# The shader core will be whatever is after the CPU cores are accounted for
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shader_idx = args.num_cpus
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system.cpu.append(shader)
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# This arbitrary address is something in the X86 I/O hole
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hsapp_gpu_map_paddr = 0xE0000000
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hsapp_pt_walker = VegaPagetableWalker()
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gpu_hsapp = HSAPacketProcessor(
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pioAddr=hsapp_gpu_map_paddr,
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numHWQueues=args.num_hw_queues,
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walker=hsapp_pt_walker,
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)
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dispatcher_exit_events = False
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if args.exit_at_gpu_task > -1:
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dispatcher_exit_events = True
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if args.exit_after_gpu_kernel > -1:
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dispatcher_exit_events = True
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dispatcher = GPUDispatcher(kernel_exit_events=dispatcher_exit_events)
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cp_pt_walker = VegaPagetableWalker()
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target_kernel = args.skip_until_gpu_kernel
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gpu_cmd_proc = GPUCommandProcessor(
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hsapp=gpu_hsapp,
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dispatcher=dispatcher,
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walker=cp_pt_walker,
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target_non_blit_kernel_id=target_kernel,
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)
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shader.dispatcher = dispatcher
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shader.gpu_cmd_proc = gpu_cmd_proc
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system.pc.south_bridge.gpu.cp = gpu_cmd_proc
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# GPU Interrupt Handler
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device_ih = AMDGPUInterruptHandler()
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system.pc.south_bridge.gpu.device_ih = device_ih
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# Setup the SDMA engines depending on device. The MMIO base addresses
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# can be found in the driver code under:
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# include/asic_reg/sdmaX/sdmaX_Y_Z_offset.h
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num_sdmas = 2
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sdma_bases = []
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sdma_sizes = []
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if args.gpu_device == "Vega10":
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num_sdmas = 2
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sdma_bases = [0x4980, 0x5180]
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sdma_sizes = [0x800] * 2
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elif args.gpu_device == "MI100":
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num_sdmas = 8
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sdma_bases = [
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0x4980,
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0x6180,
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0x78000,
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0x79000,
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0x7A000,
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0x7B000,
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0x7C000,
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0x7D000,
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]
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sdma_sizes = [0x1000] * 8
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elif args.gpu_device == "MI200" or args.gpu_device == "MI300X":
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num_sdmas = 5
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sdma_bases = [
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0x4980,
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0x6180,
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0x78000,
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0x79000,
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0x7A000,
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]
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sdma_sizes = [0x1000] * 5
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else:
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m5.util.panic(f"Unknown GPU device {args.gpu_device}")
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sdma_pt_walkers = []
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sdma_engines = []
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for sdma_idx in range(num_sdmas):
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sdma_pt_walker = VegaPagetableWalker()
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sdma_engine = SDMAEngine(
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walker=sdma_pt_walker,
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mmio_base=sdma_bases[sdma_idx],
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mmio_size=sdma_sizes[sdma_idx],
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)
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sdma_pt_walkers.append(sdma_pt_walker)
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sdma_engines.append(sdma_engine)
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system.pc.south_bridge.gpu.sdmas = sdma_engines
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# Setup PM4 packet processors
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pm4_procs = []
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pm4_procs.append(
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PM4PacketProcessor(
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ip_id=0, mmio_range=AddrRange(start=0xC000, end=0xD000)
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)
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)
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system.pc.south_bridge.gpu.pm4_pkt_procs = pm4_procs
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# GPU data path
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gpu_mem_mgr = AMDGPUMemoryManager(cache_line_size=args.cacheline_size)
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system.pc.south_bridge.gpu.memory_manager = gpu_mem_mgr
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# CPU data path (SystemHub)
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system_hub = AMDGPUSystemHub()
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shader.system_hub = system_hub
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# GPU, HSAPP, and GPUCommandProc are DMA devices
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system._dma_ports.append(gpu_hsapp)
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system._dma_ports.append(gpu_cmd_proc)
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system._dma_ports.append(system.pc.south_bridge.gpu)
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for sdma in sdma_engines:
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system._dma_ports.append(sdma)
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system._dma_ports.append(device_ih)
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for pm4_proc in pm4_procs:
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system._dma_ports.append(pm4_proc)
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system._dma_ports.append(system_hub)
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system._dma_ports.append(gpu_mem_mgr)
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system._dma_ports.append(hsapp_pt_walker)
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system._dma_ports.append(cp_pt_walker)
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for sdma_pt_walker in sdma_pt_walkers:
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system._dma_ports.append(sdma_pt_walker)
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gpu_hsapp.pio = system.iobus.mem_side_ports
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gpu_cmd_proc.pio = system.iobus.mem_side_ports
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system.pc.south_bridge.gpu.pio = system.iobus.mem_side_ports
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for sdma in sdma_engines:
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sdma.pio = system.iobus.mem_side_ports
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device_ih.pio = system.iobus.mem_side_ports
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for pm4_proc in pm4_procs:
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pm4_proc.pio = system.iobus.mem_side_ports
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system_hub.pio = system.iobus.mem_side_ports
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# Full system needs special TLBs for SQC, Scalar, and vector data ports
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args.full_system = True
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GPUTLBConfig.config_tlb_hierarchy(
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args, system, shader_idx, system.pc.south_bridge.gpu, True
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)
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# Create Ruby system using disjoint VIPER topology
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system.ruby = Disjoint_VIPER()
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system.ruby.create(args, system, system.iobus, system._dma_ports)
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# Create a seperate clock domain for Ruby
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system.ruby.clk_domain = SrcClockDomain(
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clock=args.ruby_clock, voltage_domain=system.voltage_domain
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)
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# If we are using KVM cpu, enable AVX. AVX is used in some ROCm libraries
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# such as rocBLAS which is used in higher level libraries like PyTorch.
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use_avx = False
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if ObjectList.is_kvm_cpu(TestCPUClass) and not args.disable_avx:
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# AVX also requires CR4.osxsave to be 1. These must be set together
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# of KVM will error out.
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system.workload.enable_osxsave = 1
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use_avx = True
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# These values are taken from a real CPU and are further explained here:
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# https://sandpile.org/x86/cpuid.htm#level_0000_000Dh
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avx_extended_state = [
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0x00000007,
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0x00000340,
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0x00000000,
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0x00000340,
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0x00000000,
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0x00000340,
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0x00000000,
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0x00000000,
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0x00000100,
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0x00000240,
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0x00000000,
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0x00000040,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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]
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# This modifies the default value for ECX only (4th in this array).
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# See: https://sandpile.org/x86/cpuid.htm#level_0000_0001h
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# Enables AVX, OSXSAVE, XSAVE, POPCNT, SSE4.2, SSE4.1, CMPXCHG16B,
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# and FMA.
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avx_cpu_features = [0x00020F51, 0x00000805, 0xEFDBFBFF, 0x1C803209]
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for i, cpu in enumerate(system.cpu):
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# Break once we reach the shader "CPU"
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if i == args.num_cpus:
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break
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#
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# Tie the cpu ports to the correct ruby system ports
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#
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cpu.clk_domain = system.cpu_clk_domain
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cpu.createThreads()
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cpu.createInterruptController()
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system.ruby._cpu_ports[i].connectCpuPorts(cpu)
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for j in range(len(system.cpu[i].isa)):
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system.cpu[i].isa[j].vendor_string = "AuthenticAMD"
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if use_avx:
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system.cpu[i].isa[j].ExtendedState = avx_extended_state
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system.cpu[i].isa[j].FamilyModelStepping = avx_cpu_features
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if args.host_parallel:
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# To get the KVM CPUs to run on different host CPUs, specify a
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# different event queue for each CPU. The last CPU is a GPU
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# shader and should be skipped.
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for i, cpu in enumerate(system.cpu[:-1]):
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for obj in cpu.descendants():
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obj.eventq_index = 0
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cpu.eventq_index = i + 1
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# Only enable KVM perf counters if explicitly set, as this is more
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# restrictive.
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if ObjectList.is_kvm_cpu(TestCPUClass):
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if args.kvm_perf:
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for i, cpu in enumerate(system.cpu[:-1]):
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cpu.usePerf = True
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else:
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for i, cpu in enumerate(system.cpu[:-1]):
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cpu.usePerf = False
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gpu_port_idx = (
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len(system.ruby._cpu_ports)
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- args.num_compute_units
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- args.num_sqc
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- args.num_scalar_cache
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)
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gpu_port_idx = gpu_port_idx - args.num_cp * 2
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# Connect token ports. For this we need to search through the list of all
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# sequencers, since the TCP coalescers will not necessarily be first. Only
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# TCP coalescers use a token port for back pressure.
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token_port_idx = 0
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for i in range(len(system.ruby._cpu_ports)):
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if isinstance(system.ruby._cpu_ports[i], VIPERCoalescer):
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system.cpu[shader_idx].CUs[
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token_port_idx
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].gmTokenPort = system.ruby._cpu_ports[i].gmTokenPort
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token_port_idx += 1
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wavefront_size = args.wf_size
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for i in range(args.num_compute_units):
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# The pipeline issues wavefront_size number of uncoalesced requests
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# in one GPU issue cycle. Hence wavefront_size mem ports.
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for j in range(wavefront_size):
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system.cpu[shader_idx].CUs[i].memory_port[
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j
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] = system.ruby._cpu_ports[gpu_port_idx].in_ports[j]
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gpu_port_idx += 1
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for i in range(args.num_compute_units):
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if i > 0 and not i % args.cu_per_sqc:
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gpu_port_idx += 1
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system.cpu[shader_idx].CUs[i].sqc_port = system.ruby._cpu_ports[
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gpu_port_idx
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].in_ports
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gpu_port_idx = gpu_port_idx + 1
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for i in range(args.num_compute_units):
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if i > 0 and not i % args.cu_per_scalar_cache:
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gpu_port_idx += 1
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system.cpu[shader_idx].CUs[i].scalar_port = system.ruby._cpu_ports[
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gpu_port_idx
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].in_ports
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gpu_port_idx = gpu_port_idx + 1
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return system
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