As part of recent decisions regarding namespace naming conventions, all namespaces will be changed to snake case. gem5::Debug became gem5::debug. Change-Id: Ic04606baab3317d2e58ab3ca9b37fc201c406ee8 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47305 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
254 lines
9.2 KiB
C++
254 lines
9.2 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* Copyright (c) 2016 The University of Virginia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/riscv/process.hh"
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#include <algorithm>
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#include <cstddef>
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#include <iostream>
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#include <iterator>
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#include <map>
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#include <string>
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#include <vector>
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#include "arch/riscv/isa.hh"
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#include "arch/riscv/page_size.hh"
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#include "arch/riscv/regs/int.hh"
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#include "arch/riscv/regs/misc.hh"
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#include "base/loader/elf_object.hh"
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#include "base/loader/object_file.hh"
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#include "base/logging.hh"
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#include "base/random.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Stack.hh"
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#include "mem/page_table.hh"
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#include "params/Process.hh"
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#include "sim/aux_vector.hh"
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#include "sim/process.hh"
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#include "sim/process_impl.hh"
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#include "sim/syscall_return.hh"
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#include "sim/system.hh"
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namespace gem5
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{
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using namespace RiscvISA;
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RiscvProcess::RiscvProcess(const ProcessParams ¶ms,
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loader::ObjectFile *objFile) :
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Process(params,
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new EmulationPageTable(params.name, params.pid, PageBytes),
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objFile)
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{
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fatal_if(params.useArchPT, "Arch page tables not implemented.");
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}
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RiscvProcess64::RiscvProcess64(const ProcessParams ¶ms,
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loader::ObjectFile *objFile) :
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RiscvProcess(params, objFile)
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{
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const Addr stack_base = 0x7FFFFFFFFFFFFFFFL;
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const Addr max_stack_size = 8 * 1024 * 1024;
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const Addr next_thread_stack_base = stack_base - max_stack_size;
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const Addr brk_point = roundUp(image.maxAddr(), PageBytes);
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const Addr mmap_end = 0x4000000000000000L;
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memState = std::make_shared<MemState>(this, brk_point, stack_base,
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max_stack_size, next_thread_stack_base, mmap_end);
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}
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RiscvProcess32::RiscvProcess32(const ProcessParams ¶ms,
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loader::ObjectFile *objFile) :
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RiscvProcess(params, objFile)
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{
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const Addr stack_base = 0x7FFFFFFF;
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const Addr max_stack_size = 8 * 1024 * 1024;
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const Addr next_thread_stack_base = stack_base - max_stack_size;
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const Addr brk_point = roundUp(image.maxAddr(), PageBytes);
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const Addr mmap_end = 0x40000000L;
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memState = std::make_shared<MemState>(this, brk_point, stack_base,
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max_stack_size, next_thread_stack_base, mmap_end);
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}
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void
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RiscvProcess64::initState()
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{
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Process::initState();
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argsInit<uint64_t>(PageBytes);
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for (ContextID ctx: contextIds)
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system->threads[ctx]->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
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}
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void
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RiscvProcess32::initState()
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{
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Process::initState();
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argsInit<uint32_t>(PageBytes);
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for (ContextID ctx: contextIds) {
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auto *tc = system->threads[ctx];
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tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
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PCState pc = tc->pcState();
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pc.rv32(true);
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tc->pcState(pc);
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}
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}
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template<class IntType> void
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RiscvProcess::argsInit(int pageSize)
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{
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const int RandomBytes = 16;
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const int addrSize = sizeof(IntType);
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auto *elfObject = dynamic_cast<loader::ElfObject*>(objFile);
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memState->setStackMin(memState->getStackBase());
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// Determine stack size and populate auxv
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Addr stack_top = memState->getStackMin();
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stack_top -= RandomBytes;
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for (const std::string& arg: argv)
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stack_top -= arg.size() + 1;
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for (const std::string& env: envp)
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stack_top -= env.size() + 1;
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stack_top &= -addrSize;
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std::vector<gem5::auxv::AuxVector<IntType>> auxv;
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if (elfObject != nullptr) {
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auxv.emplace_back(gem5::auxv::Entry, objFile->entryPoint());
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auxv.emplace_back(gem5::auxv::Phnum, elfObject->programHeaderCount());
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auxv.emplace_back(gem5::auxv::Phent, elfObject->programHeaderSize());
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auxv.emplace_back(gem5::auxv::Phdr, elfObject->programHeaderTable());
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auxv.emplace_back(gem5::auxv::Pagesz, PageBytes);
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auxv.emplace_back(gem5::auxv::Secure, 0);
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auxv.emplace_back(gem5::auxv::Random, stack_top);
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auxv.emplace_back(gem5::auxv::Null, 0);
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}
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stack_top -= (1 + argv.size()) * addrSize +
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(1 + envp.size()) * addrSize +
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addrSize + 2 * sizeof(IntType) * auxv.size();
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stack_top &= -2*addrSize;
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memState->setStackSize(memState->getStackBase() - stack_top);
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memState->mapRegion(roundDown(stack_top, pageSize),
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roundUp(memState->getStackSize(), pageSize), "stack");
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// Copy random bytes (for AT_RANDOM) to stack
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memState->setStackMin(memState->getStackMin() - RandomBytes);
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uint8_t at_random[RandomBytes];
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std::generate(std::begin(at_random), std::end(at_random),
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[&]{ return random_mt.random(0, 0xFF); });
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initVirtMem->writeBlob(memState->getStackMin(), at_random, RandomBytes);
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// Copy argv to stack
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std::vector<Addr> argPointers;
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for (const std::string& arg: argv) {
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memState->setStackMin(memState->getStackMin() - (arg.size() + 1));
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initVirtMem->writeString(memState->getStackMin(), arg.c_str());
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argPointers.push_back(memState->getStackMin());
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if (debug::Stack) {
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std::string wrote;
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initVirtMem->readString(wrote, argPointers.back());
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DPRINTFN("Wrote arg \"%s\" to address %p\n",
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wrote, (void*)memState->getStackMin());
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}
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}
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argPointers.push_back(0);
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// Copy envp to stack
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std::vector<Addr> envPointers;
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for (const std::string& env: envp) {
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memState->setStackMin(memState->getStackMin() - (env.size() + 1));
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initVirtMem->writeString(memState->getStackMin(), env.c_str());
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envPointers.push_back(memState->getStackMin());
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DPRINTF(Stack, "Wrote env \"%s\" to address %p\n",
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env, (void*)memState->getStackMin());
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}
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envPointers.push_back(0);
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// Align stack
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memState->setStackMin(memState->getStackMin() & -addrSize);
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// Calculate bottom of stack
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memState->setStackMin(memState->getStackMin() -
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((1 + argv.size()) * addrSize +
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(1 + envp.size()) * addrSize +
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addrSize + 2 * sizeof(IntType) * auxv.size()));
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memState->setStackMin(memState->getStackMin() & (-2 * addrSize));
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Addr sp = memState->getStackMin();
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const auto pushOntoStack =
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[this, &sp](IntType data) {
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initVirtMem->write(sp, data, ByteOrder::little);
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sp += sizeof(data);
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};
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// Push argc and argv pointers onto stack
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IntType argc = argv.size();
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DPRINTF(Stack, "Wrote argc %d to address %#x\n", argc, sp);
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pushOntoStack(argc);
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for (const Addr& argPointer: argPointers) {
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DPRINTF(Stack, "Wrote argv pointer %#x to address %#x\n",
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argPointer, sp);
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pushOntoStack(argPointer);
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}
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// Push env pointers onto stack
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for (const Addr& envPointer: envPointers) {
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DPRINTF(Stack, "Wrote envp pointer %#x to address %#x\n",
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envPointer, sp);
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pushOntoStack(envPointer);
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}
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// Push aux vector onto stack
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std::map<IntType, std::string> aux_keys = {
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{gem5::auxv::Entry, "gem5::auxv::Entry"},
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{gem5::auxv::Phnum, "gem5::auxv::Phnum"},
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{gem5::auxv::Phent, "gem5::auxv::Phent"},
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{gem5::auxv::Phdr, "gem5::auxv::Phdr"},
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{gem5::auxv::Pagesz, "gem5::auxv::Pagesz"},
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{gem5::auxv::Secure, "gem5::auxv::Secure"},
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{gem5::auxv::Random, "gem5::auxv::Random"},
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{gem5::auxv::Null, "gem5::auxv::Null"}
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};
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for (const auto &aux: auxv) {
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DPRINTF(Stack, "Wrote aux key %s to address %#x\n",
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aux_keys[aux.type], sp);
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pushOntoStack(aux.type);
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DPRINTF(Stack, "Wrote aux value %x to address %#x\n", aux.val, sp);
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pushOntoStack(aux.val);
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}
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ThreadContext *tc = system->threads[contextIds[0]];
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tc->setIntReg(StackPointerReg, memState->getStackMin());
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tc->pcState(getStartPC());
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memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
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}
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} // namespace gem5
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