Korey Sewell 226d49ef69 Merge zizzer:/bk/multiarch ...

into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/multiarch-m5

--HG--
extra : convert_revision : f3502f293f6ea44b5cf209ce2a935a25bca6054f

2006-03-08 16:54:08 -05:00

..

alpha

Working towards compiling SPARC_SE

2006-03-08 08:09:27 -05:00

mips

add explicit support for nop,ssnop, and ehb instructions

2006-03-08 16:53:44 -05:00

sparc

Working towards compiling SPARC_SE

2006-03-08 08:09:27 -05:00

isa_parser.py

Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included.

2006-03-03 15:28:25 -05:00

isa_specific.hh

Auto-generate arch/foo.hh "switch headers" in scons.

2006-02-22 22:22:06 -05:00

SConscript

Pushed ev5.hh out of the non-alpha code.

2006-03-07 14:08:01 -05:00