a3e113239b
In most cases, the microcode ROM doesn't actually do anything. The structural existence of a microcode ROM doesn't make sense in the general case, and in architectures that know they have one and need to interact with it, they can cast their decoder into an arch specific type and access the ROM that way. Change-Id: I25b67bfe65df1fdb84eb5bc894cfcb83da1ce64b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32898 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
685 lines
20 KiB
C++
685 lines
20 KiB
C++
/*
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* Copyright (c) 2010-2012, 2015, 2017, 2018, 2020 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/simple/base.hh"
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#include "arch/utility.hh"
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#include "base/cprintf.hh"
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#include "base/inifile.hh"
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#include "base/loader/symtab.hh"
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#include "base/logging.hh"
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#include "base/pollevent.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "config/the_isa.hh"
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#include "cpu/base.hh"
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#include "cpu/checker/cpu.hh"
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#include "cpu/checker/thread_context.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/pred/bpred_unit.hh"
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#include "cpu/simple/exec_context.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/smt.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Decode.hh"
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#include "debug/ExecFaulting.hh"
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#include "debug/Fetch.hh"
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#include "debug/Quiesce.hh"
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#include "mem/packet.hh"
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#include "mem/request.hh"
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#include "params/BaseSimpleCPU.hh"
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#include "sim/byteswap.hh"
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#include "sim/debug.hh"
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#include "sim/faults.hh"
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#include "sim/full_system.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace TheISA;
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BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
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: BaseCPU(p),
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curThread(0),
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branchPred(p->branchPred),
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traceData(NULL),
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inst(),
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_status(Idle)
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{
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SimpleThread *thread;
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for (unsigned i = 0; i < numThreads; i++) {
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if (FullSystem) {
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thread = new SimpleThread(this, i, p->system,
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p->itb, p->dtb, p->isa[i]);
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} else {
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thread = new SimpleThread(this, i, p->system, p->workload[i],
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p->itb, p->dtb, p->isa[i]);
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}
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threadInfo.push_back(new SimpleExecContext(this, thread));
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ThreadContext *tc = thread->getTC();
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threadContexts.push_back(tc);
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}
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if (p->checker) {
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if (numThreads != 1)
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fatal("Checker currently does not support SMT");
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BaseCPU *temp_checker = p->checker;
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checker = dynamic_cast<CheckerCPU *>(temp_checker);
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checker->setSystem(p->system);
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// Manipulate thread context
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ThreadContext *cpu_tc = threadContexts[0];
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threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
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} else {
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checker = NULL;
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}
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}
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void
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BaseSimpleCPU::init()
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{
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BaseCPU::init();
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for (auto tc : threadContexts) {
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// Initialise the ThreadContext's memory proxies
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tc->initMemProxies(tc);
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}
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}
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void
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BaseSimpleCPU::checkPcEventQueue()
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{
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Addr oldpc, pc = threadInfo[curThread]->thread->instAddr();
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do {
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oldpc = pc;
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threadInfo[curThread]->thread->pcEventQueue.service(
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oldpc, threadContexts[curThread]);
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pc = threadInfo[curThread]->thread->instAddr();
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} while (oldpc != pc);
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}
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void
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BaseSimpleCPU::swapActiveThread()
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{
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if (numThreads > 1) {
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if ((!curStaticInst || !curStaticInst->isDelayedCommit()) &&
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!threadInfo[curThread]->stayAtPC) {
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// Swap active threads
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if (!activeThreads.empty()) {
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curThread = activeThreads.front();
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activeThreads.pop_front();
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activeThreads.push_back(curThread);
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}
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}
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}
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}
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void
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BaseSimpleCPU::countInst()
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{
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SimpleExecContext& t_info = *threadInfo[curThread];
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if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) {
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t_info.numInst++;
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t_info.numInsts++;
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system->totalNumInsts++;
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t_info.thread->funcExeInst++;
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}
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t_info.numOp++;
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t_info.numOps++;
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}
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Counter
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BaseSimpleCPU::totalInsts() const
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{
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Counter total_inst = 0;
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for (auto& t_info : threadInfo) {
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total_inst += t_info->numInst;
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}
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return total_inst;
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}
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Counter
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BaseSimpleCPU::totalOps() const
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{
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Counter total_op = 0;
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for (auto& t_info : threadInfo) {
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total_op += t_info->numOp;
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}
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return total_op;
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}
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BaseSimpleCPU::~BaseSimpleCPU()
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{
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}
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void
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BaseSimpleCPU::haltContext(ThreadID thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
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}
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void
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BaseSimpleCPU::regStats()
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{
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using namespace Stats;
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BaseCPU::regStats();
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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SimpleExecContext& t_info = *threadInfo[tid];
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std::string thread_str = name();
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if (numThreads > 1)
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thread_str += ".thread" + std::to_string(tid);
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t_info.numInsts
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.name(thread_str + ".committedInsts")
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.desc("Number of instructions committed")
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;
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t_info.numOps
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.name(thread_str + ".committedOps")
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.desc("Number of ops (including micro ops) committed")
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;
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t_info.numIntAluAccesses
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.name(thread_str + ".num_int_alu_accesses")
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.desc("Number of integer alu accesses")
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;
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t_info.numFpAluAccesses
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.name(thread_str + ".num_fp_alu_accesses")
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.desc("Number of float alu accesses")
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;
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t_info.numVecAluAccesses
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.name(thread_str + ".num_vec_alu_accesses")
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.desc("Number of vector alu accesses")
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;
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t_info.numCallsReturns
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.name(thread_str + ".num_func_calls")
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.desc("number of times a function call or return occured")
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;
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t_info.numCondCtrlInsts
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.name(thread_str + ".num_conditional_control_insts")
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.desc("number of instructions that are conditional controls")
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;
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t_info.numIntInsts
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.name(thread_str + ".num_int_insts")
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.desc("number of integer instructions")
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;
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t_info.numFpInsts
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.name(thread_str + ".num_fp_insts")
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.desc("number of float instructions")
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;
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t_info.numVecInsts
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.name(thread_str + ".num_vec_insts")
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.desc("number of vector instructions")
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;
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t_info.numIntRegReads
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.name(thread_str + ".num_int_register_reads")
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.desc("number of times the integer registers were read")
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;
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t_info.numIntRegWrites
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.name(thread_str + ".num_int_register_writes")
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.desc("number of times the integer registers were written")
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;
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t_info.numFpRegReads
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.name(thread_str + ".num_fp_register_reads")
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.desc("number of times the floating registers were read")
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;
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t_info.numFpRegWrites
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.name(thread_str + ".num_fp_register_writes")
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.desc("number of times the floating registers were written")
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;
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t_info.numVecRegReads
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.name(thread_str + ".num_vec_register_reads")
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.desc("number of times the vector registers were read")
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;
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t_info.numVecRegWrites
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.name(thread_str + ".num_vec_register_writes")
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.desc("number of times the vector registers were written")
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;
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t_info.numCCRegReads
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.name(thread_str + ".num_cc_register_reads")
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.desc("number of times the CC registers were read")
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.flags(nozero)
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;
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t_info.numCCRegWrites
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.name(thread_str + ".num_cc_register_writes")
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.desc("number of times the CC registers were written")
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.flags(nozero)
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;
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t_info.numMemRefs
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.name(thread_str + ".num_mem_refs")
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.desc("number of memory refs")
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;
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t_info.numStoreInsts
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.name(thread_str + ".num_store_insts")
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.desc("Number of store instructions")
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;
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t_info.numLoadInsts
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.name(thread_str + ".num_load_insts")
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.desc("Number of load instructions")
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;
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t_info.notIdleFraction
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.name(thread_str + ".not_idle_fraction")
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.desc("Percentage of non-idle cycles")
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;
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t_info.idleFraction
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.name(thread_str + ".idle_fraction")
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.desc("Percentage of idle cycles")
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;
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t_info.numBusyCycles
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.name(thread_str + ".num_busy_cycles")
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.desc("Number of busy cycles")
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;
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t_info.numIdleCycles
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.name(thread_str + ".num_idle_cycles")
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.desc("Number of idle cycles")
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;
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t_info.icacheStallCycles
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.name(thread_str + ".icache_stall_cycles")
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.desc("ICache total stall cycles")
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.prereq(t_info.icacheStallCycles)
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;
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t_info.dcacheStallCycles
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.name(thread_str + ".dcache_stall_cycles")
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.desc("DCache total stall cycles")
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.prereq(t_info.dcacheStallCycles)
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;
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t_info.statExecutedInstType
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.init(Enums::Num_OpClass)
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.name(thread_str + ".op_class")
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.desc("Class of executed instruction")
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.flags(total | pdf | dist)
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;
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for (unsigned i = 0; i < Num_OpClasses; ++i) {
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t_info.statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
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}
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t_info.idleFraction = constant(1.0) - t_info.notIdleFraction;
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t_info.numIdleCycles = t_info.idleFraction * numCycles;
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t_info.numBusyCycles = t_info.notIdleFraction * numCycles;
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t_info.numBranches
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.name(thread_str + ".Branches")
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.desc("Number of branches fetched")
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.prereq(t_info.numBranches);
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t_info.numPredictedBranches
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.name(thread_str + ".predictedBranches")
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.desc("Number of branches predicted as taken")
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.prereq(t_info.numPredictedBranches);
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t_info.numBranchMispred
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.name(thread_str + ".BranchMispred")
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.desc("Number of branch mispredictions")
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.prereq(t_info.numBranchMispred);
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}
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}
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void
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BaseSimpleCPU::resetStats()
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{
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BaseCPU::resetStats();
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for (auto &thread_info : threadInfo) {
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thread_info->notIdleFraction = (_status != Idle);
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}
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}
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void
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BaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
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{
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assert(_status == Idle || _status == Running);
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threadInfo[tid]->thread->serialize(cp);
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}
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void
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BaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid)
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{
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threadInfo[tid]->thread->unserialize(cp);
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}
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void
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change_thread_state(ThreadID tid, int activate, int priority)
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{
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}
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void
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BaseSimpleCPU::wakeup(ThreadID tid)
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{
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getCpuAddrMonitor(tid)->gotWakeup = true;
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if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
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DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid);
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threadInfo[tid]->thread->activate();
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}
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}
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void
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BaseSimpleCPU::traceFault()
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{
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if (DTRACE(ExecFaulting)) {
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traceData->setFaulting(true);
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} else {
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delete traceData;
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traceData = NULL;
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}
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}
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void
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BaseSimpleCPU::checkForInterrupts()
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{
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SimpleExecContext&t_info = *threadInfo[curThread];
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SimpleThread* thread = t_info.thread;
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ThreadContext* tc = thread->getTC();
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if (checkInterrupts(curThread)) {
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Fault interrupt = interrupts[curThread]->getInterrupt();
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if (interrupt != NoFault) {
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t_info.fetchOffset = 0;
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interrupts[curThread]->updateIntrInfo();
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interrupt->invoke(tc);
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thread->decoder.reset();
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}
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}
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}
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void
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BaseSimpleCPU::setupFetchRequest(const RequestPtr &req)
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{
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SimpleExecContext &t_info = *threadInfo[curThread];
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SimpleThread* thread = t_info.thread;
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Addr instAddr = thread->instAddr();
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Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
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// set up memory request for instruction fetch
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DPRINTF(Fetch, "Fetch: Inst PC:%08p, Fetch PC:%08p\n", instAddr, fetchPC);
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req->setVirt(fetchPC, sizeof(MachInst), Request::INST_FETCH,
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instMasterId(), instAddr);
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}
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void
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BaseSimpleCPU::preExecute()
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{
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SimpleExecContext &t_info = *threadInfo[curThread];
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SimpleThread* thread = t_info.thread;
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// maintain $r0 semantics
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thread->setIntReg(ZeroReg, 0);
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// resets predicates
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t_info.setPredicate(true);
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t_info.setMemAccPredicate(true);
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// check for instruction-count-based events
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thread->comInstEventQueue.serviceEvents(t_info.numInst);
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// decode the instruction
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TheISA::PCState pcState = thread->pcState();
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if (isRomMicroPC(pcState.microPC())) {
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t_info.stayAtPC = false;
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curStaticInst = thread->decoder.fetchRomMicroop(
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pcState.microPC(), curMacroStaticInst);
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} else if (!curMacroStaticInst) {
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//We're not in the middle of a macro instruction
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StaticInstPtr instPtr = NULL;
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TheISA::Decoder *decoder = &(thread->decoder);
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//Predecode, ie bundle up an ExtMachInst
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//If more fetch data is needed, pass it in.
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Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset;
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//if (decoder->needMoreBytes())
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decoder->moreBytes(pcState, fetchPC, inst);
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//else
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// decoder->process();
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//Decode an instruction if one is ready. Otherwise, we'll have to
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//fetch beyond the MachInst at the current pc.
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instPtr = decoder->decode(pcState);
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if (instPtr) {
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t_info.stayAtPC = false;
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thread->pcState(pcState);
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} else {
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t_info.stayAtPC = true;
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t_info.fetchOffset += sizeof(MachInst);
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}
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//If we decoded an instruction and it's microcoded, start pulling
|
|
//out micro ops
|
|
if (instPtr && instPtr->isMacroop()) {
|
|
curMacroStaticInst = instPtr;
|
|
curStaticInst =
|
|
curMacroStaticInst->fetchMicroop(pcState.microPC());
|
|
} else {
|
|
curStaticInst = instPtr;
|
|
}
|
|
} else {
|
|
//Read the next micro op from the macro op
|
|
curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
|
|
}
|
|
|
|
//If we decoded an instruction this "tick", record information about it.
|
|
if (curStaticInst) {
|
|
#if TRACING_ON
|
|
traceData = tracer->getInstRecord(curTick(), thread->getTC(),
|
|
curStaticInst, thread->pcState(), curMacroStaticInst);
|
|
|
|
DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
|
|
curStaticInst->getName(), curStaticInst->machInst);
|
|
#endif // TRACING_ON
|
|
}
|
|
|
|
if (branchPred && curStaticInst &&
|
|
curStaticInst->isControl()) {
|
|
// Use a fake sequence number since we only have one
|
|
// instruction in flight at the same time.
|
|
const InstSeqNum cur_sn(0);
|
|
t_info.predPC = thread->pcState();
|
|
const bool predict_taken(
|
|
branchPred->predict(curStaticInst, cur_sn, t_info.predPC,
|
|
curThread));
|
|
|
|
if (predict_taken)
|
|
++t_info.numPredictedBranches;
|
|
}
|
|
}
|
|
|
|
void
|
|
BaseSimpleCPU::postExecute()
|
|
{
|
|
SimpleExecContext &t_info = *threadInfo[curThread];
|
|
|
|
assert(curStaticInst);
|
|
|
|
TheISA::PCState pc = threadContexts[curThread]->pcState();
|
|
Addr instAddr = pc.instAddr();
|
|
|
|
if (curStaticInst->isMemRef()) {
|
|
t_info.numMemRefs++;
|
|
}
|
|
|
|
if (curStaticInst->isLoad()) {
|
|
++t_info.numLoad;
|
|
}
|
|
|
|
if (curStaticInst->isControl()) {
|
|
++t_info.numBranches;
|
|
}
|
|
|
|
/* Power model statistics */
|
|
//integer alu accesses
|
|
if (curStaticInst->isInteger()){
|
|
t_info.numIntAluAccesses++;
|
|
t_info.numIntInsts++;
|
|
}
|
|
|
|
//float alu accesses
|
|
if (curStaticInst->isFloating()){
|
|
t_info.numFpAluAccesses++;
|
|
t_info.numFpInsts++;
|
|
}
|
|
|
|
//vector alu accesses
|
|
if (curStaticInst->isVector()){
|
|
t_info.numVecAluAccesses++;
|
|
t_info.numVecInsts++;
|
|
}
|
|
|
|
//number of function calls/returns to get window accesses
|
|
if (curStaticInst->isCall() || curStaticInst->isReturn()){
|
|
t_info.numCallsReturns++;
|
|
}
|
|
|
|
//the number of branch predictions that will be made
|
|
if (curStaticInst->isCondCtrl()){
|
|
t_info.numCondCtrlInsts++;
|
|
}
|
|
|
|
//result bus acceses
|
|
if (curStaticInst->isLoad()){
|
|
t_info.numLoadInsts++;
|
|
}
|
|
|
|
if (curStaticInst->isStore() || curStaticInst->isAtomic()){
|
|
t_info.numStoreInsts++;
|
|
}
|
|
/* End power model statistics */
|
|
|
|
t_info.statExecutedInstType[curStaticInst->opClass()]++;
|
|
|
|
if (FullSystem)
|
|
traceFunctions(instAddr);
|
|
|
|
if (traceData) {
|
|
traceData->dump();
|
|
delete traceData;
|
|
traceData = NULL;
|
|
}
|
|
|
|
// Call CPU instruction commit probes
|
|
probeInstCommit(curStaticInst, instAddr);
|
|
}
|
|
|
|
void
|
|
BaseSimpleCPU::advancePC(const Fault &fault)
|
|
{
|
|
SimpleExecContext &t_info = *threadInfo[curThread];
|
|
SimpleThread* thread = t_info.thread;
|
|
|
|
const bool branching(thread->pcState().branching());
|
|
|
|
//Since we're moving to a new pc, zero out the offset
|
|
t_info.fetchOffset = 0;
|
|
if (fault != NoFault) {
|
|
curMacroStaticInst = StaticInst::nullStaticInstPtr;
|
|
fault->invoke(threadContexts[curThread], curStaticInst);
|
|
thread->decoder.reset();
|
|
} else {
|
|
if (curStaticInst) {
|
|
if (curStaticInst->isLastMicroop())
|
|
curMacroStaticInst = StaticInst::nullStaticInstPtr;
|
|
TheISA::PCState pcState = thread->pcState();
|
|
TheISA::advancePC(pcState, curStaticInst);
|
|
thread->pcState(pcState);
|
|
}
|
|
}
|
|
|
|
if (branchPred && curStaticInst && curStaticInst->isControl()) {
|
|
// Use a fake sequence number since we only have one
|
|
// instruction in flight at the same time.
|
|
const InstSeqNum cur_sn(0);
|
|
|
|
if (t_info.predPC == thread->pcState()) {
|
|
// Correctly predicted branch
|
|
branchPred->update(cur_sn, curThread);
|
|
} else {
|
|
// Mis-predicted branch
|
|
branchPred->squash(cur_sn, thread->pcState(), branching, curThread);
|
|
++t_info.numBranchMispred;
|
|
}
|
|
}
|
|
}
|