SConscript:
easier to fix than temporarily remove
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
mem needed for both fullsys and syscall
dev/baddev.cc:
fix for new mem system
dev/io_device.cc:
fix typo
dev/io_device.hh:
PioDevice needs to be a memobject
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
fix for new mem systems
dev/platform.cc:
dev/platform.hh:
dev/tsunami.cc:
dev/tsunami.hh:
rather than the platform have a pointer to pciconfig, go the other
way so all devices are the same and can have a platform pointer
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart8250.cc:
python/m5/objects/AlphaConsole.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/Device.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/System.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
fixes for newmem
--HG--
extra : convert_revision : b7b67e19095cca64889f6307725aa2f3d84c7105
152 lines
4.4 KiB
C++
152 lines
4.4 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Isa Fake Device implementation
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "dev/isa_fake.hh"
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#include "mem/packet.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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IsaFake::IsaFake(Params *p)
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: BasicPioDevice(p)
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{
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pioSize = p->pio_size;
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}
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Tick
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IsaFake::read(Packet &pkt)
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{
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assert(pkt.result == Unknown);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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pkt.time = curTick + pioDelay;
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DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size);
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uint8_t *data8;
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uint16_t *data16;
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uint32_t *data32;
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uint64_t *data64;
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switch (pkt.size) {
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case sizeof(uint64_t):
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if (!pkt.data) {
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data64 = new uint64_t;
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pkt.data = (uint8_t*)data64;
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} else {
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data64 = (uint64_t*)pkt.data;
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}
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*data64 = 0xFFFFFFFFFFFFFFFFULL;
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break;
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case sizeof(uint32_t):
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if (!pkt.data) {
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data32 = new uint32_t;
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pkt.data = (uint8_t*)data32;
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} else {
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data32 = (uint32_t*)pkt.data;
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}
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*data32 = 0xFFFFFFFF;
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break;
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case sizeof(uint16_t):
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if (!pkt.data) {
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data16 = new uint16_t;
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pkt.data = (uint8_t*)data16;
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} else {
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data16 = (uint16_t*)pkt.data;
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}
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*data16 = 0xFFFF;
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break;
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case sizeof(uint8_t):
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if (!pkt.data) {
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data8 = new uint8_t;
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pkt.data = data8;
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} else {
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data8 = (uint8_t*)pkt.data;
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}
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*data8 = 0xFF;
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break;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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pkt.result = Success;
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return pioDelay;
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}
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Tick
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IsaFake::write(Packet &pkt)
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{
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pkt.time = curTick + pioDelay;
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DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt.addr, pkt.size);
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pkt.result = Success;
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return pioDelay;
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
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Param<Addr> pio_addr;
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Param<Tick> pio_latency;
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Param<Addr> pio_size;
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SimObjectParam<Platform *> platform;
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SimObjectParam<System *> system;
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END_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
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BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake)
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INIT_PARAM(pio_addr, "Device Address"),
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INIT_PARAM(pio_latency, "Programmed IO latency"),
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INIT_PARAM(pio_size, "Size of address range"),
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INIT_PARAM(platform, "platform"),
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INIT_PARAM(system, "system object")
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END_INIT_SIM_OBJECT_PARAMS(IsaFake)
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CREATE_SIM_OBJECT(IsaFake)
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{
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IsaFake::Params *p = new IsaFake::Params;
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p->name = getInstanceName();
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p->pio_addr = pio_addr;
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p->pio_delay = pio_latency;
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p->pio_size = pio_size;
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p->platform = platform;
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p->system = system;
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return new IsaFake(p);
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}
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REGISTER_SIM_OBJECT("IsaFake", IsaFake)
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