Alexandru Dutu 1f539f13c3 mem: Page Table map api modification ...

This patch adds uncacheable/cacheable and read-only/read-write attributes to
the map method of PageTableBase. It also modifies the constructor of TlbEntry
structs for all architectures to consider the new attributes.

2014-11-23 18:01:09 -08:00

..

arch

mem: Page Table map api modification

2014-11-23 18:01:09 -08:00

base

vnc: Add a conversion function for bgr888.

2014-11-17 01:45:42 -08:00

cpu

kvm, x86: Adding support for SE mode execution

2014-11-23 18:01:08 -08:00

dev

x86: pc: Put a stub IO device at port 0xed which the kernel can use for delays.

2014-11-21 17:22:02 -08:00

doc

cpu: `Minor' in-order CPU model

2014-07-23 16:09:04 -05:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

kern

misc: Move AddrRangeList from port.hh to addr_range.hh

2014-10-16 05:49:59 -04:00

mem

mem: Page Table map api modification

2014-11-23 18:01:09 -08:00

proto

mem: change the namespace Message to ProtoMessage

2014-09-01 16:55:46 -05:00

python

sim: Sort SimObject descendants and ports

2014-11-12 09:05:21 -05:00

sim

mem: Page Table map api modification

2014-11-23 18:01:09 -08:00

unittest

unittest: Fix build errors

2014-01-30 12:21:58 -06:00

Doxyfile

Doxygen: Update the version of the Doxyfile

2012-10-11 06:38:42 -04:00

SConscript

arch,x86,mem: Dynamically determine the ISA for Ruby store check

2014-10-16 05:49:44 -04:00