78524bda56
This constant is, first, a #define, and second only used in one place. In that one place, it appears that the code it guards is no longer necessary in general. It was originally written to avoid refetching a block of data that you're still in, even if you've moved slightly farther in it because you're skipping the next instruction due to an annulled branch delay slot. In reality however, in SPARC, the one ISA I'm aware of which has this sort of branching behavior, the PC state object will correctly determine that no branch is happening in these cases. Code lower down in the loop will then recompute where fetching should continue based on the next PC, automatically skipping the annulled branch slot without misinterpretting the gap as a branch. This change therefore also removes this block of code. Change-Id: I820ebc9df10aeb4fcb69c12f6a784e9ec616743c Reviewed-on: https://gem5-review.googlesource.com/6821 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
72 lines
2.6 KiB
C++
72 lines
2.6 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* Copyright (c) 2009 The University of Edinburgh
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Timothy M. Jones
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* Gabe Black
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* Stephen Hines
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*/
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#ifndef __ARCH_POWER_ISA_TRAITS_HH__
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#define __ARCH_POWER_ISA_TRAITS_HH__
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#include "arch/power/types.hh"
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#include "base/types.hh"
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#include "cpu/static_inst_fwd.hh"
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namespace BigEndianGuest {}
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namespace PowerISA
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{
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using namespace BigEndianGuest;
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StaticInstPtr decodeInst(ExtMachInst);
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const Addr PageShift = 12;
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const Addr PageBytes = ULL(1) << PageShift;
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const Addr Page_Mask = ~(PageBytes - 1);
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const Addr PageOffset = PageBytes - 1;
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const Addr PteShift = 3;
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const Addr NPtePageShift = PageShift - PteShift;
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const Addr NPtePage = ULL(1) << NPtePageShift;
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const Addr PteMask = NPtePage - 1;
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const int MachineBytes = 4;
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// Memory accesses can be unaligned
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const bool HasUnalignedMemAcc = true;
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const bool CurThreadInfoImplemented = false;
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const int CurThreadInfoReg = -1;
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} // namespace PowerISA
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#endif // __ARCH_POWER_ISA_TRAITS_HH__
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