1088f0c4ac
These files aren't a collection of miscellaneous stuff, they're the definition of the Logger interface, and a few utility macros for calling into that interface (panic, warn, etc.). Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1 Reviewed-on: https://gem5-review.googlesource.com/6226 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
142 lines
3.5 KiB
C++
142 lines
3.5 KiB
C++
/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* Copyright (c) 2009 The University of Edinburgh
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Timothy M. Jones
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*/
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#ifndef __ARCH_POWER_ISA_HH__
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#define __ARCH_POWER_ISA_HH__
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#include "arch/power/registers.hh"
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#include "arch/power/types.hh"
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#include "base/logging.hh"
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#include "cpu/reg_class.hh"
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#include "sim/sim_object.hh"
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struct PowerISAParams;
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class ThreadContext;
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class Checkpoint;
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class EventManager;
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namespace PowerISA
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{
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class ISA : public SimObject
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{
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protected:
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MiscReg dummy;
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MiscReg miscRegs[NumMiscRegs];
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public:
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typedef PowerISAParams Params;
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void
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clear()
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{
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}
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MiscReg
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readMiscRegNoEffect(int misc_reg) const
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{
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fatal("Power does not currently have any misc regs defined\n");
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return dummy;
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}
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MiscReg
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readMiscReg(int misc_reg, ThreadContext *tc)
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{
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fatal("Power does not currently have any misc regs defined\n");
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return dummy;
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}
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void
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setMiscRegNoEffect(int misc_reg, const MiscReg &val)
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{
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fatal("Power does not currently have any misc regs defined\n");
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}
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void
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setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
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{
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fatal("Power does not currently have any misc regs defined\n");
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}
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RegId flattenRegId(const RegId& regId) const { return regId; }
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int
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flattenIntIndex(int reg) const
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{
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return reg;
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}
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int
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flattenFloatIndex(int reg) const
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{
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return reg;
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}
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int
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flattenVecIndex(int reg) const
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{
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return reg;
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}
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int
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flattenVecElemIndex(int reg) const
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{
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return reg;
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}
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// dummy
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int
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flattenCCIndex(int reg) const
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{
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return reg;
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}
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int
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flattenMiscIndex(int reg) const
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{
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return reg;
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}
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void startup(ThreadContext *tc) {}
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/// Explicitly import the otherwise hidden startup
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using SimObject::startup;
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const Params *params() const;
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ISA(Params *p);
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};
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} // namespace PowerISA
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#endif // __ARCH_POWER_ISA_HH__
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