1be246bbe3
The PM4 packet processor is handling all non-HSA GPU packets such as packets for (un)mapping HSA queues. This commit pulls many Linux structs and defines out into their own files for clarity. Finally, it implements the VMID related functions in AMDGPU device. Change-Id: I5f0057209305404df58aff2c4cd07762d1a31690 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53068 Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Maintainer: Matt Sinclair <mattdsinclair@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
70 lines
3.7 KiB
C++
70 lines
3.7 KiB
C++
/*
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* Copyright (c) 2021 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef __DEV_AMDGPU_PM4_MMIO_HH__
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#define __DEV_AMDGPU_PM4_MMIO_HH__
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namespace gem5
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{
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#define mmCP_RB0_BASE 0x1040
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#define mmCP_RB0_CNTL 0x1041
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#define mmCP_RB_WPTR_POLL_ADDR_LO 0x1046
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#define mmCP_RB_WPTR_POLL_ADDR_HI 0x1047
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#define mmCP_RB_VMID 0x1051
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#define mmCP_RB0_RPTR_ADDR 0x1043
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#define mmCP_RB0_RPTR_ADDR_HI 0x1044
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#define mmCP_RB0_WPTR 0x1054
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#define mmCP_RB0_WPTR_HI 0x1055
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#define mmCP_RB_DOORBELL_CONTROL 0x1059
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#define mmCP_RB_DOORBELL_RANGE_LOWER 0x105a
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#define mmCP_RB_DOORBELL_RANGE_UPPER 0x105b
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#define mmCP_RB0_BASE_HI 0x10b1
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#define mmCP_HQD_ACTIVE 0x1247
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#define mmCP_HQD_VMID 0x1248
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#define mmCP_HQD_PQ_BASE 0x124d
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#define mmCP_HQD_PQ_BASE_HI 0x124e
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#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254
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#define mmCP_HQD_PQ_RPTR 0x124f
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#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250
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#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251
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#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252
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#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253
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#define mmCP_HQD_IB_CONTROL 0x125a
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#define mmCP_HQD_PQ_WPTR_LO 0x127b
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#define mmCP_HQD_PQ_WPTR_HI 0x127c
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} // namespace gem5
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#endif // __DEV_AMDGPU_PM4_MMIO_HH__
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