19bf5c4f33
--since int is only 4 bytes, while ssize_t is 8 bytes in 64bit system. so 0x80000000 is regarded as negative value. Jira Issue:: https://gem5.atlassian.net/browse/GEM5-1203 Change-Id: I74b3785b29751f777f5e154692fa60bf62b37b9f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58649 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
947 lines
30 KiB
C++
947 lines
30 KiB
C++
/*
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* Copyright (c) 2011-2012, 2014, 2018-2019, 2021 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_LSQ_HH__
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#define __CPU_O3_LSQ_HH__
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#include <cassert>
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#include <cstdint>
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#include <list>
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#include <map>
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#include <queue>
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#include <vector>
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#include "arch/generic/mmu.hh"
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#include "arch/generic/tlb.hh"
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#include "base/flags.hh"
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#include "base/types.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/o3/dyn_inst_ptr.hh"
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#include "cpu/utils.hh"
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#include "enums/SMTQueuePolicy.hh"
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#include "mem/port.hh"
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#include "sim/sim_object.hh"
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namespace gem5
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{
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struct BaseO3CPUParams;
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namespace o3
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{
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class CPU;
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class IEW;
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class LSQUnit;
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class LSQ
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{
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public:
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class LSQRequest;
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/**
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* DcachePort class for the load/store queue.
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*/
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class DcachePort : public RequestPort
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{
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protected:
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/** Pointer to LSQ. */
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LSQ *lsq;
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CPU *cpu;
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public:
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/** Default constructor. */
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DcachePort(LSQ *_lsq, CPU *_cpu);
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protected:
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/** Timing version of receive. Handles writing back and
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* completing the load or store that has returned from
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* memory. */
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virtual bool recvTimingResp(PacketPtr pkt);
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virtual void recvTimingSnoopReq(PacketPtr pkt);
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virtual void
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recvFunctionalSnoop(PacketPtr pkt)
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{
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// @todo: Is there a need for potential invalidation here?
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}
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/** Handles doing a retry of the previous send. */
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virtual void recvReqRetry();
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/**
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* As this CPU requires snooping to maintain the load store queue
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* change the behaviour from the base CPU port.
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*
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* @return true since we have to snoop
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*/
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virtual bool isSnooping() const { return true; }
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};
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/** Memory operation metadata.
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* This class holds the information about a memory operation. It lives
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* from initiateAcc to resource deallocation at commit or squash.
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* LSQRequest objects are owned by the LQ/SQ Entry in the LSQUnit that
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* holds the operation. In addition, the LSQRequest is a TranslationState,
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* therefore, upon squash, there must be a defined ownership transferal
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* in case the LSQ resources are deallocated before the TLB is done using
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* the TranslationState.
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* If that happens, the LSQRequest will be self-owned, and responsible to
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* detect that its services are no longer required and self-destruct.
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*
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* Lifetime of a LSQRequest:
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* +--------------------+
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* |LSQ creates and owns|
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* +--------------------+
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* |
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* +--------------------+
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* | Initate translation|
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* +--------------------+
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* |
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* ___^___
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* ___/ \___
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* ______/ Squashed? \
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* | \___ ___/
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* | \___ ___/
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* | v
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* | |
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* | +--------------------+
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* | | Translation done |
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* | +--------------------+
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* | |
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* | +--------------------+
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* | | Send packet |<------+
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* | +--------------------+ |
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* | | |
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* | ___^___ |
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* | ___/ \___ |
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* | ____/ Squashed? \ |
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* | | \___ ___/ |
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* | | \___ ___/ |
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* | | v |
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* | | | |
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* | | ___^___ |
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* | | ___/ \___ |
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* | | / Done? \__________|
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* | | \___ ___/
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* | | \___ ___/
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* | | v
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* | | |
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* | | +--------------------+
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* | | | Manage stuff |
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* | | | Free resources |
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* | | +--------------------+
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* | |
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* | | +--------------------+
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* | | | self owned |
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* | +->| on recvTimingResp |
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* | | free resources |
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* | +--------------------+
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* |
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* | +----------------------+
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* | | self owned (Trans) |
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* +-->| on TranslationFinish |
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* | free resources |
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* +----------------------+
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*
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*
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*/
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class LSQRequest : public BaseMMU::Translation, public Packet::SenderState
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{
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protected:
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typedef uint32_t FlagsStorage;
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typedef Flags<FlagsStorage> FlagsType;
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enum Flag : FlagsStorage
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{
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IsLoad = 0x00000001,
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/** True if this request needs to writeBack to register.
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* Will be set in case of load or a store/atomic
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* that writes registers (SC)
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*/
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WriteBackToRegister = 0x00000002,
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Delayed = 0x00000004,
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IsSplit = 0x00000008,
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/** True if any translation has been sent to TLB. */
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TranslationStarted = 0x00000010,
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/** True if there are un-replied outbound translations.. */
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TranslationFinished = 0x00000020,
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Sent = 0x00000040,
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Retry = 0x00000080,
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Complete = 0x00000100,
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/** Ownership tracking flags. */
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/** Translation squashed. */
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TranslationSquashed = 0x00000200,
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/** Request discarded */
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Discarded = 0x00000400,
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/** LSQ resources freed. */
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LSQEntryFreed = 0x00000800,
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/** Store written back. */
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WritebackScheduled = 0x00001000,
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WritebackDone = 0x00002000,
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/** True if this is an atomic request */
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IsAtomic = 0x00004000
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};
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FlagsType flags;
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enum class State
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{
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NotIssued,
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Translation,
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Request,
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Fault,
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PartialFault,
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};
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State _state;
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void setState(const State& newState) { _state = newState; }
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uint32_t numTranslatedFragments;
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uint32_t numInTranslationFragments;
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void markDelayed() override { flags.set(Flag::Delayed); }
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bool isDelayed() { return flags.isSet(Flag::Delayed); }
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public:
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LSQUnit& _port;
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const DynInstPtr _inst;
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uint32_t _taskId;
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PacketDataPtr _data;
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std::vector<PacketPtr> _packets;
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std::vector<RequestPtr> _reqs;
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std::vector<Fault> _fault;
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uint64_t* _res;
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const Addr _addr;
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const uint32_t _size;
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const Request::Flags _flags;
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std::vector<bool> _byteEnable;
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uint32_t _numOutstandingPackets;
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AtomicOpFunctorPtr _amo_op;
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protected:
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LSQUnit* lsqUnit() { return &_port; }
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LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad);
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LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad,
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const Addr& addr, const uint32_t& size,
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const Request::Flags& flags_, PacketDataPtr data=nullptr,
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uint64_t* res=nullptr, AtomicOpFunctorPtr amo_op=nullptr);
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bool
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isLoad() const
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{
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return flags.isSet(Flag::IsLoad);
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}
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bool
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isAtomic() const
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{
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return flags.isSet(Flag::IsAtomic);
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}
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/** Install the request in the LQ/SQ. */
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void install();
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bool squashed() const override;
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/** Release the LSQRequest.
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* Notify the sender state that the request it points to is not valid
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* anymore. Understand if the request is orphan (self-managed) and if
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* so, mark it as freed, else destroy it, as this means
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* the end of its life cycle.
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* An LSQRequest is orphan when its resources are released
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* but there is any in-flight translation request to the TLB or access
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* request to the memory.
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*/
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void
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release(Flag reason)
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{
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assert(reason == Flag::LSQEntryFreed || reason == Flag::Discarded);
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if (!isAnyOutstandingRequest()) {
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delete this;
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} else {
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flags.set(reason);
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}
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}
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/** Helper function used to add a (sub)request, given its address
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* `addr`, size `size` and byte-enable mask `byteEnable`.
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*
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* The request is only added if there is at least one active
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* element in the mask.
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*/
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void addReq(Addr addr, unsigned size,
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const std::vector<bool>& byte_enable);
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/** Destructor.
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* The LSQRequest owns the request. If the packet has already been
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* sent, the sender state will be deleted upon receiving the reply.
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*/
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virtual ~LSQRequest();
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public:
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/** Convenience getters/setters. */
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/** @{ */
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/** Set up Context numbers. */
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void
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setContext(const ContextID& context_id)
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{
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req()->setContext(context_id);
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}
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const DynInstPtr& instruction() { return _inst; }
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/** Set up virtual request.
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* For a previously allocated Request objects.
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*/
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void
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setVirt(Addr vaddr, unsigned size, Request::Flags flags_,
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RequestorID requestor_id, Addr pc)
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{
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req()->setVirt(vaddr, size, flags_, requestor_id, pc);
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}
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ContextID contextId() const;
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void
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taskId(const uint32_t& v)
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{
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_taskId = v;
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for (auto& r: _reqs)
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r->taskId(v);
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}
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uint32_t taskId() const { return _taskId; }
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RequestPtr req(int idx = 0) { return _reqs.at(idx); }
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const RequestPtr req(int idx = 0) const { return _reqs.at(idx); }
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Addr getVaddr(int idx = 0) const { return req(idx)->getVaddr(); }
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virtual void initiateTranslation() = 0;
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PacketPtr packet(int idx = 0) { return _packets.at(idx); }
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virtual PacketPtr
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mainPacket()
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{
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assert (_packets.size() == 1);
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return packet();
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}
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virtual RequestPtr
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mainReq()
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{
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assert (_reqs.size() == 1);
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return req();
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}
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/**
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* Test if there is any in-flight translation or mem access request
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*/
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bool
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isAnyOutstandingRequest()
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{
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return numInTranslationFragments > 0 ||
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_numOutstandingPackets > 0 ||
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(flags.isSet(Flag::WritebackScheduled) &&
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!flags.isSet(Flag::WritebackDone));
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}
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/**
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* Test if the LSQRequest has been released, i.e. self-owned.
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* An LSQRequest manages itself when the resources on the LSQ are freed
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* but the translation is still going on and the LSQEntry was freed.
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*/
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bool
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isReleased()
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{
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return flags.isSet(Flag::LSQEntryFreed) ||
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flags.isSet(Flag::Discarded);
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}
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bool
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isSplit() const
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{
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return flags.isSet(Flag::IsSplit);
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}
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bool
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needWBToRegister() const
|
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{
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return flags.isSet(Flag::WriteBackToRegister);
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}
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/** @} */
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virtual bool recvTimingResp(PacketPtr pkt) = 0;
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virtual void sendPacketToCache() = 0;
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virtual void buildPackets() = 0;
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/**
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* Memory mapped IPR accesses
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*/
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virtual Cycles handleLocalAccess(
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gem5::ThreadContext *thread, PacketPtr pkt) = 0;
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/**
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* Test if the request accesses a particular cache line.
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*/
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virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask) = 0;
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|
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/** Update the status to reflect that a packet was sent. */
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void
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packetSent()
|
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{
|
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flags.set(Flag::Sent);
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}
|
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/** Update the status to reflect that a packet was not sent.
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* When a packet fails to be sent, we mark the request as needing a
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* retry. Note that Retry flag is sticky.
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*/
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void
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packetNotSent()
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{
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flags.set(Flag::Retry);
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flags.clear(Flag::Sent);
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}
|
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|
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void sendFragmentToTranslation(int i);
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bool
|
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isComplete()
|
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{
|
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return flags.isSet(Flag::Complete);
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}
|
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|
|
bool
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isInTranslation()
|
|
{
|
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return _state == State::Translation;
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}
|
|
|
|
bool
|
|
isTranslationComplete()
|
|
{
|
|
return flags.isSet(Flag::TranslationStarted) &&
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!isInTranslation();
|
|
}
|
|
|
|
bool
|
|
isTranslationBlocked()
|
|
{
|
|
return _state == State::Translation &&
|
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flags.isSet(Flag::TranslationStarted) &&
|
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!flags.isSet(Flag::TranslationFinished);
|
|
}
|
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|
|
bool
|
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isSent()
|
|
{
|
|
return flags.isSet(Flag::Sent);
|
|
}
|
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|
|
bool
|
|
isPartialFault()
|
|
{
|
|
return _state == State::PartialFault;
|
|
}
|
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|
|
bool
|
|
isMemAccessRequired()
|
|
{
|
|
return (_state == State::Request ||
|
|
(isPartialFault() && isLoad()));
|
|
}
|
|
|
|
void
|
|
setStateToFault()
|
|
{
|
|
setState(State::Fault);
|
|
}
|
|
|
|
/**
|
|
* The LSQ entry is cleared
|
|
*/
|
|
void
|
|
freeLSQEntry()
|
|
{
|
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release(Flag::LSQEntryFreed);
|
|
}
|
|
|
|
/**
|
|
* The request is discarded (e.g. partial store-load forwarding)
|
|
*/
|
|
void
|
|
discard()
|
|
{
|
|
release(Flag::Discarded);
|
|
}
|
|
|
|
void
|
|
packetReplied()
|
|
{
|
|
assert(_numOutstandingPackets > 0);
|
|
_numOutstandingPackets--;
|
|
if (_numOutstandingPackets == 0 && isReleased())
|
|
delete this;
|
|
}
|
|
|
|
void
|
|
writebackScheduled()
|
|
{
|
|
assert(!flags.isSet(Flag::WritebackScheduled));
|
|
flags.set(Flag::WritebackScheduled);
|
|
}
|
|
|
|
void
|
|
writebackDone()
|
|
{
|
|
flags.set(Flag::WritebackDone);
|
|
/* If the lsq resources are already free */
|
|
if (isReleased()) {
|
|
delete this;
|
|
}
|
|
}
|
|
|
|
void
|
|
squashTranslation()
|
|
{
|
|
assert(numInTranslationFragments == 0);
|
|
flags.set(Flag::TranslationSquashed);
|
|
/* If we are on our own, self-destruct. */
|
|
if (isReleased()) {
|
|
delete this;
|
|
}
|
|
}
|
|
|
|
void
|
|
complete()
|
|
{
|
|
flags.set(Flag::Complete);
|
|
}
|
|
|
|
virtual std::string name() const { return "LSQRequest"; }
|
|
};
|
|
|
|
class SingleDataRequest : public LSQRequest
|
|
{
|
|
public:
|
|
SingleDataRequest(LSQUnit* port, const DynInstPtr& inst,
|
|
bool isLoad, const Addr& addr, const uint32_t& size,
|
|
const Request::Flags& flags_, PacketDataPtr data=nullptr,
|
|
uint64_t* res=nullptr, AtomicOpFunctorPtr amo_op=nullptr) :
|
|
LSQRequest(port, inst, isLoad, addr, size, flags_, data, res,
|
|
std::move(amo_op)) {}
|
|
|
|
virtual ~SingleDataRequest() {}
|
|
virtual void initiateTranslation();
|
|
virtual void finish(const Fault &fault, const RequestPtr &req,
|
|
gem5::ThreadContext* tc, BaseMMU::Mode mode);
|
|
virtual bool recvTimingResp(PacketPtr pkt);
|
|
virtual void sendPacketToCache();
|
|
virtual void buildPackets();
|
|
virtual Cycles handleLocalAccess(
|
|
gem5::ThreadContext *thread, PacketPtr pkt);
|
|
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask);
|
|
virtual std::string name() const { return "SingleDataRequest"; }
|
|
};
|
|
|
|
// This class extends SingleDataRequest for the purpose
|
|
// of allowing special requests (eg Hardware transactional memory, TLB
|
|
// shootdowns) to bypass irrelevant system elements like translation &
|
|
// squashing.
|
|
class UnsquashableDirectRequest : public SingleDataRequest
|
|
{
|
|
public:
|
|
UnsquashableDirectRequest(LSQUnit* port, const DynInstPtr& inst,
|
|
const Request::Flags& flags_);
|
|
inline virtual ~UnsquashableDirectRequest() {}
|
|
virtual void initiateTranslation();
|
|
virtual void finish(const Fault &fault, const RequestPtr &req,
|
|
gem5::ThreadContext* tc, BaseMMU::Mode mode);
|
|
virtual std::string
|
|
name() const
|
|
{
|
|
return "UnsquashableDirectRequest";
|
|
}
|
|
};
|
|
|
|
class SplitDataRequest : public LSQRequest
|
|
{
|
|
protected:
|
|
uint32_t numFragments;
|
|
uint32_t numReceivedPackets;
|
|
RequestPtr _mainReq;
|
|
PacketPtr _mainPacket;
|
|
|
|
public:
|
|
SplitDataRequest(LSQUnit* port, const DynInstPtr& inst,
|
|
bool isLoad, const Addr& addr, const uint32_t& size,
|
|
const Request::Flags & flags_, PacketDataPtr data=nullptr,
|
|
uint64_t* res=nullptr) :
|
|
LSQRequest(port, inst, isLoad, addr, size, flags_, data, res,
|
|
nullptr),
|
|
numFragments(0),
|
|
numReceivedPackets(0),
|
|
_mainReq(nullptr),
|
|
_mainPacket(nullptr)
|
|
{
|
|
flags.set(Flag::IsSplit);
|
|
}
|
|
virtual ~SplitDataRequest()
|
|
{
|
|
if (_mainReq) {
|
|
_mainReq = nullptr;
|
|
}
|
|
if (_mainPacket) {
|
|
delete _mainPacket;
|
|
_mainPacket = nullptr;
|
|
}
|
|
}
|
|
virtual void finish(const Fault &fault, const RequestPtr &req,
|
|
gem5::ThreadContext* tc, BaseMMU::Mode mode);
|
|
virtual bool recvTimingResp(PacketPtr pkt);
|
|
virtual void initiateTranslation();
|
|
virtual void sendPacketToCache();
|
|
virtual void buildPackets();
|
|
|
|
virtual Cycles handleLocalAccess(
|
|
gem5::ThreadContext *thread, PacketPtr pkt);
|
|
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask);
|
|
|
|
virtual RequestPtr mainReq();
|
|
virtual PacketPtr mainPacket();
|
|
virtual std::string name() const { return "SplitDataRequest"; }
|
|
};
|
|
|
|
/** Constructs an LSQ with the given parameters. */
|
|
LSQ(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams ¶ms);
|
|
|
|
/** Returns the name of the LSQ. */
|
|
std::string name() const;
|
|
|
|
/** Sets the pointer to the list of active threads. */
|
|
void setActiveThreads(std::list<ThreadID> *at_ptr);
|
|
|
|
/** Perform sanity checks after a drain. */
|
|
void drainSanityCheck() const;
|
|
/** Has the LSQ drained? */
|
|
bool isDrained() const;
|
|
/** Takes over execution from another CPU's thread. */
|
|
void takeOverFrom();
|
|
|
|
/** Number of entries needed for the given amount of threads.*/
|
|
int entryAmount(ThreadID num_threads);
|
|
|
|
/** Ticks the LSQ. */
|
|
void tick();
|
|
|
|
/** Inserts a load into the LSQ. */
|
|
void insertLoad(const DynInstPtr &load_inst);
|
|
/** Inserts a store into the LSQ. */
|
|
void insertStore(const DynInstPtr &store_inst);
|
|
|
|
/** Executes a load. */
|
|
Fault executeLoad(const DynInstPtr &inst);
|
|
|
|
/** Executes a store. */
|
|
Fault executeStore(const DynInstPtr &inst);
|
|
|
|
/**
|
|
* Commits loads up until the given sequence number for a specific thread.
|
|
*/
|
|
void commitLoads(InstSeqNum &youngest_inst, ThreadID tid);
|
|
|
|
/**
|
|
* Commits stores up until the given sequence number for a specific thread.
|
|
*/
|
|
void commitStores(InstSeqNum &youngest_inst, ThreadID tid);
|
|
|
|
/**
|
|
* Attempts to write back stores until all cache ports are used or the
|
|
* interface becomes blocked.
|
|
*/
|
|
void writebackStores();
|
|
/** Same as above, but only for one thread. */
|
|
void writebackStores(ThreadID tid);
|
|
|
|
/**
|
|
* Squash instructions from a thread until the specified sequence number.
|
|
*/
|
|
void squash(const InstSeqNum &squashed_num, ThreadID tid);
|
|
|
|
/** Returns whether or not there was a memory ordering violation. */
|
|
bool violation();
|
|
|
|
/**
|
|
* Returns whether or not there was a memory ordering violation for a
|
|
* specific thread.
|
|
*/
|
|
bool violation(ThreadID tid);
|
|
|
|
/** Gets the instruction that caused the memory ordering violation. */
|
|
DynInstPtr getMemDepViolator(ThreadID tid);
|
|
|
|
/** Returns the head index of the load queue for a specific thread. */
|
|
int getLoadHead(ThreadID tid);
|
|
|
|
/** Returns the sequence number of the head of the load queue. */
|
|
InstSeqNum getLoadHeadSeqNum(ThreadID tid);
|
|
|
|
/** Returns the head index of the store queue. */
|
|
int getStoreHead(ThreadID tid);
|
|
|
|
/** Returns the sequence number of the head of the store queue. */
|
|
InstSeqNum getStoreHeadSeqNum(ThreadID tid);
|
|
|
|
/** Returns the number of instructions in all of the queues. */
|
|
int getCount();
|
|
/** Returns the number of instructions in the queues of one thread. */
|
|
int getCount(ThreadID tid);
|
|
|
|
/** Returns the total number of loads in the load queue. */
|
|
int numLoads();
|
|
/** Returns the total number of loads for a single thread. */
|
|
int numLoads(ThreadID tid);
|
|
|
|
/** Returns the total number of stores in the store queue. */
|
|
int numStores();
|
|
/** Returns the total number of stores for a single thread. */
|
|
int numStores(ThreadID tid);
|
|
|
|
|
|
// hardware transactional memory
|
|
|
|
int numHtmStarts(ThreadID tid) const;
|
|
int numHtmStops(ThreadID tid) const;
|
|
void resetHtmStartsStops(ThreadID tid);
|
|
uint64_t getLatestHtmUid(ThreadID tid) const;
|
|
void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid);
|
|
|
|
/** Returns the number of free load entries. */
|
|
unsigned numFreeLoadEntries();
|
|
|
|
/** Returns the number of free store entries. */
|
|
unsigned numFreeStoreEntries();
|
|
|
|
/** Returns the number of free entries for a specific thread. */
|
|
unsigned numFreeEntries(ThreadID tid);
|
|
|
|
/** Returns the number of free entries in the LQ for a specific thread. */
|
|
unsigned numFreeLoadEntries(ThreadID tid);
|
|
|
|
/** Returns the number of free entries in the SQ for a specific thread. */
|
|
unsigned numFreeStoreEntries(ThreadID tid);
|
|
|
|
/** Returns if the LSQ is full (either LQ or SQ is full). */
|
|
bool isFull();
|
|
/**
|
|
* Returns if the LSQ is full for a specific thread (either LQ or SQ is
|
|
* full).
|
|
*/
|
|
bool isFull(ThreadID tid);
|
|
|
|
/** Returns if the LSQ is empty (both LQ and SQ are empty). */
|
|
bool isEmpty() const;
|
|
/** Returns if all of the LQs are empty. */
|
|
bool lqEmpty() const;
|
|
/** Returns if all of the SQs are empty. */
|
|
bool sqEmpty() const;
|
|
|
|
/** Returns if any of the LQs are full. */
|
|
bool lqFull();
|
|
/** Returns if the LQ of a given thread is full. */
|
|
bool lqFull(ThreadID tid);
|
|
|
|
/** Returns if any of the SQs are full. */
|
|
bool sqFull();
|
|
/** Returns if the SQ of a given thread is full. */
|
|
bool sqFull(ThreadID tid);
|
|
|
|
/**
|
|
* Returns if the LSQ is stalled due to a memory operation that must be
|
|
* replayed.
|
|
*/
|
|
bool isStalled();
|
|
/**
|
|
* Returns if the LSQ of a specific thread is stalled due to a memory
|
|
* operation that must be replayed.
|
|
*/
|
|
bool isStalled(ThreadID tid);
|
|
|
|
/** Returns whether or not there are any stores to write back to memory. */
|
|
bool hasStoresToWB();
|
|
|
|
/** Returns whether or not a specific thread has any stores to write back
|
|
* to memory.
|
|
*/
|
|
bool hasStoresToWB(ThreadID tid);
|
|
|
|
/** Returns the number of stores a specific thread has to write back. */
|
|
int numStoresToWB(ThreadID tid);
|
|
|
|
/** Returns if the LSQ will write back to memory this cycle. */
|
|
bool willWB();
|
|
/** Returns if the LSQ of a specific thread will write back to memory this
|
|
* cycle.
|
|
*/
|
|
bool willWB(ThreadID tid);
|
|
|
|
/** Debugging function to print out all instructions. */
|
|
void dumpInsts() const;
|
|
/** Debugging function to print out instructions from a specific thread. */
|
|
void dumpInsts(ThreadID tid) const;
|
|
|
|
/** Executes a read operation, using the load specified at the load
|
|
* index.
|
|
*/
|
|
Fault read(LSQRequest* request, ssize_t load_idx);
|
|
|
|
/** Executes a store operation, using the store specified at the store
|
|
* index.
|
|
*/
|
|
Fault write(LSQRequest* request, uint8_t *data, ssize_t store_idx);
|
|
|
|
/**
|
|
* Retry the previous send that failed.
|
|
*/
|
|
void recvReqRetry();
|
|
|
|
void completeDataAccess(PacketPtr pkt);
|
|
/**
|
|
* Handles writing back and completing the load or store that has
|
|
* returned from memory.
|
|
*
|
|
* @param pkt Response packet from the memory sub-system
|
|
*/
|
|
bool recvTimingResp(PacketPtr pkt);
|
|
|
|
void recvTimingSnoopReq(PacketPtr pkt);
|
|
|
|
Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
|
|
unsigned int size, Addr addr, Request::Flags flags,
|
|
uint64_t *res, AtomicOpFunctorPtr amo_op,
|
|
const std::vector<bool>& byte_enable);
|
|
|
|
/** The CPU pointer. */
|
|
CPU *cpu;
|
|
|
|
/** The IEW stage pointer. */
|
|
IEW *iewStage;
|
|
|
|
/** Is D-cache blocked? */
|
|
bool cacheBlocked() const;
|
|
/** Set D-cache blocked status */
|
|
void cacheBlocked(bool v);
|
|
/** Is any store port available to use? */
|
|
bool cachePortAvailable(bool is_load) const;
|
|
/** Another store port is in use */
|
|
void cachePortBusy(bool is_load);
|
|
|
|
RequestPort &getDataPort() { return dcachePort; }
|
|
|
|
protected:
|
|
/** D-cache is blocked */
|
|
bool _cacheBlocked;
|
|
/** The number of cache ports available each cycle (stores only). */
|
|
int cacheStorePorts;
|
|
/** The number of used cache ports in this cycle by stores. */
|
|
int usedStorePorts;
|
|
/** The number of cache ports available each cycle (loads only). */
|
|
int cacheLoadPorts;
|
|
/** The number of used cache ports in this cycle by loads. */
|
|
int usedLoadPorts;
|
|
|
|
|
|
/** The LSQ policy for SMT mode. */
|
|
SMTQueuePolicy lsqPolicy;
|
|
|
|
/** Auxiliary function to calculate per-thread max LSQ allocation limit.
|
|
* Depending on a policy, number of entries and possibly number of threads
|
|
* and threshold, this function calculates how many resources each thread
|
|
* can occupy at most.
|
|
*/
|
|
static uint32_t
|
|
maxLSQAllocation(SMTQueuePolicy pol, uint32_t entries,
|
|
uint32_t numThreads, uint32_t SMTThreshold)
|
|
{
|
|
if (pol == SMTQueuePolicy::Dynamic) {
|
|
return entries;
|
|
} else if (pol == SMTQueuePolicy::Partitioned) {
|
|
//@todo:make work if part_amt doesnt divide evenly.
|
|
return entries / numThreads;
|
|
} else if (pol == SMTQueuePolicy::Threshold) {
|
|
//Divide up by threshold amount
|
|
//@todo: Should threads check the max and the total
|
|
//amount of the LSQ
|
|
return SMTThreshold;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/** List of Active Threads in System. */
|
|
std::list<ThreadID> *activeThreads;
|
|
|
|
/** Total Size of LQ Entries. */
|
|
unsigned LQEntries;
|
|
/** Total Size of SQ Entries. */
|
|
unsigned SQEntries;
|
|
|
|
/** Max LQ Size - Used to Enforce Sharing Policies. */
|
|
unsigned maxLQEntries;
|
|
|
|
/** Max SQ Size - Used to Enforce Sharing Policies. */
|
|
unsigned maxSQEntries;
|
|
|
|
/** Data port. */
|
|
DcachePort dcachePort;
|
|
|
|
/** The LSQ units for individual threads. */
|
|
std::vector<LSQUnit> thread;
|
|
|
|
/** Number of Threads. */
|
|
ThreadID numThreads;
|
|
};
|
|
|
|
} // namespace o3
|
|
} // namespace gem5
|
|
|
|
#endif // __CPU_O3_LSQ_HH__
|