79a93f3429
The main restriction with this design is it results in one ISA target per board. The ISA is declared per core. To make the design simpler it's assumed a Processor (a collection of cores) are all of the same ISA. As each board has one processor, this also means a board is typically tied to one ISA per simulation. In order to remain backwards compatible and maintain the standard library APIs, this patch adds a `--main-isa` parameter which will determine what `gem5.runtime.get_runtime_isa` returns in cases where mutliple ISAs are compiled in. When setting the ISA in a simulation (via the Processor or Cores), the user may, as before, choose not to and, in this case, the `gem5.runtime.get_runtime_isa` function is used. The `gem5.runtime.get_runtime_isa` function is an intermediate step which should be removed in future versions of gem5 (users should specify precisely what ISA they want via configuration scripts). For this reason it throws a warning when used and should not be heavily relied upon. It is deprecated. Change-Id: Ia76541bfa9a5a4b6b86401309281849b49dc724b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55423 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
100 lines
3.9 KiB
Python
100 lines
3.9 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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"""
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This gem5 configuation script creates a simple board to run an ARM
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"hello world" binary.
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This is setup is the close to the simplest setup possible using the gem5
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library. It does not contain any kind of caching, IO, or any non-essential
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components.
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Usage
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-----
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```
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scons build/ARM/gem5.opt
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./build/ARM/gem5.opt configs/gem5_library/arm-hello.py
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```
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"""
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from gem5.isas import ISA
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from gem5.utils.requires import requires
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from gem5.resources.resource import Resource
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from gem5.components.memory import SingleChannelDDR3_1600
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from gem5.components.processors.cpu_types import CPUTypes
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from gem5.components.boards.simple_board import SimpleBoard
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from gem5.components.cachehierarchies.classic.no_cache import NoCache
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from gem5.components.processors.simple_processor import SimpleProcessor
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from gem5.simulate.simulator import Simulator
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# This check ensures the gem5 binary is compiled to the ARM ISA target. If not,
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# an exception will be thrown.
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requires(isa_required=ISA.ARM)
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# In this setup we don't have a cache. `NoCache` can be used for such setups.
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cache_hierarchy = NoCache()
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# We use a single channel DDR3_1600 memory system
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memory = SingleChannelDDR3_1600(size="32MB")
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# We use a simple Timing processor with one core.
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processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.ARM, num_cores=1)
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# The gem5 library simble board which can be used to run simple SE-mode
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# simulations.
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board = SimpleBoard(
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clk_freq="3GHz",
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
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)
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# Here we set the workload. In this case we want to run a simple "Hello World!"
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# program compiled to the ARM ISA. The `Resource` class will automatically
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# download the binary from the gem5 Resources cloud bucket if it's not already
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# present.
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board.set_se_binary_workload(
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# The `Resource` class reads the `resources.json` file from the gem5
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# resources repository:
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# https://gem5.googlesource.com/public/gem5-resource.
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# Any resource specified in this file will be automatically retrieved.
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# At the time of writing, this file is a WIP and does not contain all
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# resources. Jira ticket: https://gem5.atlassian.net/browse/GEM5-1096
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Resource("arm-hello64-static")
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)
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# Lastly we run the simulation.
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simulator = Simulator(board=board, full_system=False)
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simulator.run()
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print(
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"Exiting @ tick {} because {}.".format(
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simulator.get_current_tick(),
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simulator.get_last_exit_event_cause(),
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)
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)
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