Yu-Cheng Chang bcf455755e arch-riscv,dev: Update the PLIC implementation (#886) ...

Update the PLIC based on the
[riscv-plic-spec](https://github.com/riscv/riscv-plic-spec) in the PR:
- Support customized PLIC hardID and privilege mode configuration
- Backward compatable with the n_contexts parameter, will generate the
config like {0,M}, {0,S}, {1,M} ...

Change-Id: Ibff736827edb7c97921e01fa27f503574a27a562

2024-02-26 10:32:53 -08:00

..

arch

arch-riscv: Fix fflags behavior of float inst. in O3 CPU (#868)

2024-02-22 08:33:34 -08:00

base

base: Add a check for edge case

2024-01-23 11:35:54 -08:00

cpu

cpu-o3, arch: Fix SMT bug arising from v23.0 and make gem5 more robust with SMT (#828)

2024-02-19 08:52:31 +00:00

dev

arch-riscv,dev: Update the PLIC implementation (#886)

2024-02-26 10:32:53 -08:00

doc

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doxygen

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gpu-compute

gpu-compute: Remove unused and redundant functions

2024-02-09 12:17:24 -06:00

kern

misc: Fix 'maybe-uninitialized' warn turn off (#706)

2023-12-21 18:45:56 -08:00

learning_gem5

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

mem

mem-ruby: Fix possible dirty line loss in CHI when ReadShared hit on UD line (#791)

2024-02-26 10:06:17 -08:00

proto

scons: Use Kconfig to configure gem5.

2023-11-23 08:26:10 +08:00

python

arch-riscv,dev: Update the PLIC implementation (#886)

2024-02-26 10:32:53 -08:00

sim

sim: Updating Process::Map (#835)

2024-02-05 12:17:05 -08:00

sst

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

systemc

systemc: Reduce unnecessary backdoor request in atomic transaction (#795)

2024-02-05 11:08:20 -08:00

Doxyfile

misc: Change version information to develop for v24.0

2023-12-27 12:29:52 -08:00

Kconfig

scons: Add new config option HAVE_CAPSTONE to Kconfig

2023-11-23 08:26:11 +08:00

SConscript

python: Add importer to standalone gem5py_m5

2023-09-28 11:22:33 -07:00