32df25e426
This change updates the HBMCtrl such that both pseudo channels can be in separate states (read or write) at the same time. In addition, the controller queues are now always split in two halves for both pseudo channels. Change-Id: Ifb599e611ad99f6c511baaf245bad2b5c9210a86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65491 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
800 lines
26 KiB
C++
800 lines
26 KiB
C++
/*
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* Copyright (c) 2012-2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2013 Amin Farmahini-Farahani
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* MemCtrl declaration
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*/
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#ifndef __MEM_CTRL_HH__
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#define __MEM_CTRL_HH__
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#include <deque>
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#include <string>
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#include <unordered_set>
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#include <utility>
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#include <vector>
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#include "base/callback.hh"
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#include "base/statistics.hh"
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#include "enums/MemSched.hh"
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#include "mem/qos/mem_ctrl.hh"
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#include "mem/qport.hh"
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#include "params/MemCtrl.hh"
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#include "sim/eventq.hh"
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namespace gem5
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{
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namespace memory
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{
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class MemInterface;
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class DRAMInterface;
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class NVMInterface;
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/**
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* A burst helper helps organize and manage a packet that is larger than
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* the memory burst size. A system packet that is larger than the burst size
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* is split into multiple packets and all those packets point to
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* a single burst helper such that we know when the whole packet is served.
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*/
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class BurstHelper
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{
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public:
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/** Number of bursts requred for a system packet **/
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const unsigned int burstCount;
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/** Number of bursts serviced so far for a system packet **/
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unsigned int burstsServiced;
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BurstHelper(unsigned int _burstCount)
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: burstCount(_burstCount), burstsServiced(0)
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{ }
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};
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/**
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* A memory packet stores packets along with the timestamp of when
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* the packet entered the queue, and also the decoded address.
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*/
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class MemPacket
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{
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public:
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/** When did request enter the controller */
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const Tick entryTime;
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/** When will request leave the controller */
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Tick readyTime;
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/** This comes from the outside world */
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const PacketPtr pkt;
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/** RequestorID associated with the packet */
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const RequestorID _requestorId;
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const bool read;
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/** Does this packet access DRAM?*/
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const bool dram;
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/** pseudo channel num*/
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const uint8_t pseudoChannel;
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/** Will be populated by address decoder */
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const uint8_t rank;
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const uint8_t bank;
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const uint32_t row;
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/**
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* Bank id is calculated considering banks in all the ranks
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* eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
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* bankId = 8 --> rank1, bank0
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*/
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const uint16_t bankId;
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/**
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* The starting address of the packet.
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* This address could be unaligned to burst size boundaries. The
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* reason is to keep the address offset so we can accurately check
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* incoming read packets with packets in the write queue.
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*/
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Addr addr;
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/**
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* The size of this dram packet in bytes
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* It is always equal or smaller than the burst size
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*/
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unsigned int size;
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/**
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* A pointer to the BurstHelper if this MemPacket is a split packet
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* If not a split packet (common case), this is set to NULL
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*/
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BurstHelper* burstHelper;
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/**
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* QoS value of the encapsulated packet read at queuing time
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*/
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uint8_t _qosValue;
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/**
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* Set the packet QoS value
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* (interface compatibility with Packet)
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*/
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inline void qosValue(const uint8_t qv) { _qosValue = qv; }
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/**
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* Get the packet QoS value
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* (interface compatibility with Packet)
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*/
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inline uint8_t qosValue() const { return _qosValue; }
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/**
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* Get the packet RequestorID
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* (interface compatibility with Packet)
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*/
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inline RequestorID requestorId() const { return _requestorId; }
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/**
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* Get the packet size
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* (interface compatibility with Packet)
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*/
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inline unsigned int getSize() const { return size; }
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/**
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* Get the packet address
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* (interface compatibility with Packet)
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*/
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inline Addr getAddr() const { return addr; }
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/**
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* Return true if its a read packet
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* (interface compatibility with Packet)
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*/
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inline bool isRead() const { return read; }
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/**
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* Return true if its a write packet
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* (interface compatibility with Packet)
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*/
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inline bool isWrite() const { return !read; }
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/**
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* Return true if its a DRAM access
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*/
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inline bool isDram() const { return dram; }
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MemPacket(PacketPtr _pkt, bool is_read, bool is_dram, uint8_t _channel,
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uint8_t _rank, uint8_t _bank, uint32_t _row, uint16_t bank_id,
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Addr _addr, unsigned int _size)
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: entryTime(curTick()), readyTime(curTick()), pkt(_pkt),
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_requestorId(pkt->requestorId()),
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read(is_read), dram(is_dram), pseudoChannel(_channel), rank(_rank),
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bank(_bank), row(_row), bankId(bank_id), addr(_addr), size(_size),
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burstHelper(NULL), _qosValue(_pkt->qosValue())
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{ }
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};
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// The memory packets are store in a multiple dequeue structure,
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// based on their QoS priority
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typedef std::deque<MemPacket*> MemPacketQueue;
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/**
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* The memory controller is a single-channel memory controller capturing
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* the most important timing constraints associated with a
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* contemporary controller. For multi-channel memory systems, the controller
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* is combined with a crossbar model, with the channel address
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* interleaving taking part in the crossbar.
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*
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* As a basic design principle, this controller
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* model is not cycle callable, but instead uses events to: 1) decide
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* when new decisions can be made, 2) when resources become available,
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* 3) when things are to be considered done, and 4) when to send
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* things back. The controller interfaces to media specific interfaces
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* to enable flexible topoloties.
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* Through these simple principles, the model delivers
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* high performance, and lots of flexibility, allowing users to
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* evaluate the system impact of a wide range of memory technologies.
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*
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* For more details, please see Hansson et al, "Simulating DRAM
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* controllers for future system architecture exploration",
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* Proc. ISPASS, 2014. If you use this model as part of your research
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* please cite the paper.
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*
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*/
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class MemCtrl : public qos::MemCtrl
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{
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protected:
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// For now, make use of a queued response port to avoid dealing with
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// flow control for the responses being sent back
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class MemoryPort : public QueuedResponsePort
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{
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RespPacketQueue queue;
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MemCtrl& ctrl;
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public:
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MemoryPort(const std::string& name, MemCtrl& _ctrl);
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void disableSanityCheck();
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protected:
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Tick recvAtomic(PacketPtr pkt) override;
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Tick recvAtomicBackdoor(
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PacketPtr pkt, MemBackdoorPtr &backdoor) override;
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void recvFunctional(PacketPtr pkt) override;
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void recvMemBackdoorReq(const MemBackdoorReq &req,
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MemBackdoorPtr &backdoor) override;
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bool recvTimingReq(PacketPtr) override;
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AddrRangeList getAddrRanges() const override;
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};
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/**
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* Our incoming port, for a multi-ported controller add a crossbar
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* in front of it
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*/
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MemoryPort port;
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/**
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* Remember if the memory system is in timing mode
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*/
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bool isTimingMode;
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/**
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* Remember if we have to retry a request when available.
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*/
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bool retryRdReq;
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bool retryWrReq;
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/**
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* Bunch of things requires to setup "events" in gem5
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* When event "respondEvent" occurs for example, the method
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* processRespondEvent is called; no parameters are allowed
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* in these methods
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*/
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virtual void processNextReqEvent(MemInterface* mem_intr,
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MemPacketQueue& resp_queue,
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EventFunctionWrapper& resp_event,
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EventFunctionWrapper& next_req_event,
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bool& retry_wr_req);
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EventFunctionWrapper nextReqEvent;
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virtual void processRespondEvent(MemInterface* mem_intr,
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MemPacketQueue& queue,
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EventFunctionWrapper& resp_event,
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bool& retry_rd_req);
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EventFunctionWrapper respondEvent;
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/**
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* Check if the read queue has room for more entries
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*
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* @param pkt_count The number of entries needed in the read queue
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* @return true if read queue is full, false otherwise
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*/
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bool readQueueFull(unsigned int pkt_count) const;
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/**
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* Check if the write queue has room for more entries
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*
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* @param pkt_count The number of entries needed in the write queue
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* @return true if write queue is full, false otherwise
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*/
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bool writeQueueFull(unsigned int pkt_count) const;
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/**
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* When a new read comes in, first check if the write q has a
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* pending request to the same address.\ If not, decode the
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* address to populate rank/bank/row, create one or mutliple
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* "mem_pkt", and push them to the back of the read queue.\
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* If this is the only
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* read request in the system, schedule an event to start
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* servicing it.
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*
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* @param pkt The request packet from the outside world
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* @param pkt_count The number of memory bursts the pkt
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* @param mem_intr The memory interface this pkt will
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* eventually go to
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* @return if all the read pkts are already serviced by wrQ
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*/
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bool addToReadQueue(PacketPtr pkt, unsigned int pkt_count,
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MemInterface* mem_intr);
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/**
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* Decode the incoming pkt, create a mem_pkt and push to the
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* back of the write queue. \If the write q length is more than
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* the threshold specified by the user, ie the queue is beginning
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* to get full, stop reads, and start draining writes.
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*
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* @param pkt The request packet from the outside world
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* @param pkt_count The number of memory bursts the pkt
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* @param mem_intr The memory interface this pkt will
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* eventually go to
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*/
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void addToWriteQueue(PacketPtr pkt, unsigned int pkt_count,
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MemInterface* mem_intr);
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/**
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* Actually do the burst based on media specific access function.
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* Update bus statistics when complete.
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*
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* @param mem_pkt The memory packet created from the outside world pkt
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* @param mem_intr The memory interface to access
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* @return Time when the command was issued
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*
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*/
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virtual Tick doBurstAccess(MemPacket* mem_pkt, MemInterface* mem_intr);
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/**
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* When a packet reaches its "readyTime" in the response Q,
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* use the "access()" method in AbstractMemory to actually
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* create the response packet, and send it back to the outside
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* world requestor.
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*
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* @param pkt The packet from the outside world
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* @param static_latency Static latency to add before sending the packet
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* @param mem_intr the memory interface to access
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*/
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virtual void accessAndRespond(PacketPtr pkt, Tick static_latency,
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MemInterface* mem_intr);
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/**
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* Determine if there is a packet that can issue.
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*
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* @param pkt The packet to evaluate
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*/
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virtual bool packetReady(MemPacket* pkt, MemInterface* mem_intr);
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/**
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* Calculate the minimum delay used when scheduling a read-to-write
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* transision.
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* @param return minimum delay
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*/
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virtual Tick minReadToWriteDataGap();
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/**
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* Calculate the minimum delay used when scheduling a write-to-read
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* transision.
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* @param return minimum delay
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*/
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virtual Tick minWriteToReadDataGap();
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/**
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* The memory schduler/arbiter - picks which request needs to
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* go next, based on the specified policy such as FCFS or FR-FCFS
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* and moves it to the head of the queue.
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* Prioritizes accesses to the same rank as previous burst unless
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* controller is switching command type.
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*
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* @param queue Queued requests to consider
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* @param extra_col_delay Any extra delay due to a read/write switch
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* @param mem_intr the memory interface to choose from
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* @return an iterator to the selected packet, else queue.end()
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*/
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virtual MemPacketQueue::iterator chooseNext(MemPacketQueue& queue,
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Tick extra_col_delay, MemInterface* mem_intr);
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/**
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* For FR-FCFS policy reorder the read/write queue depending on row buffer
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* hits and earliest bursts available in memory
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*
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* @param queue Queued requests to consider
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* @param extra_col_delay Any extra delay due to a read/write switch
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* @return an iterator to the selected packet, else queue.end()
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*/
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virtual std::pair<MemPacketQueue::iterator, Tick>
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chooseNextFRFCFS(MemPacketQueue& queue, Tick extra_col_delay,
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MemInterface* mem_intr);
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/**
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* Calculate burst window aligned tick
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*
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* @param cmd_tick Initial tick of command
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* @return burst window aligned tick
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*/
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Tick getBurstWindow(Tick cmd_tick);
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/**
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* Used for debugging to observe the contents of the queues.
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*/
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void printQs() const;
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/**
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* Burst-align an address.
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*
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* @param addr The potentially unaligned address
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* @param mem_intr The DRAM interface this pkt belongs to
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*
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* @return An address aligned to a memory burst
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*/
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virtual Addr burstAlign(Addr addr, MemInterface* mem_intr) const;
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/**
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* Check if mem pkt's size is sane
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*
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* @param mem_pkt memory packet
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* @param mem_intr memory interface
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* @return An address aligned to a memory burst
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*/
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virtual bool pktSizeCheck(MemPacket* mem_pkt,
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MemInterface* mem_intr) const;
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/**
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* The controller's main read and write queues,
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* with support for QoS reordering
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*/
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std::vector<MemPacketQueue> readQueue;
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std::vector<MemPacketQueue> writeQueue;
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/**
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* To avoid iterating over the write queue to check for
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* overlapping transactions, maintain a set of burst addresses
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* that are currently queued. Since we merge writes to the same
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* location we never have more than one address to the same burst
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* address.
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*/
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std::unordered_set<Addr> isInWriteQueue;
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/**
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* Response queue where read packets wait after we're done working
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* with them, but it's not time to send the response yet. The
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* responses are stored separately mostly to keep the code clean
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* and help with events scheduling. For all logical purposes such
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* as sizing the read queue, this and the main read queue need to
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* be added together.
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*/
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std::deque<MemPacket*> respQueue;
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/**
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* Holds count of commands issued in burst window starting at
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* defined Tick. This is used to ensure that the command bandwidth
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* does not exceed the allowable media constraints.
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*/
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std::unordered_multiset<Tick> burstTicks;
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/**
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+ * Create pointer to interface of the actual memory media when connected
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+ */
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MemInterface* dram;
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virtual AddrRangeList getAddrRanges();
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/**
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* The following are basic design parameters of the memory
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* controller, and are initialized based on parameter values.
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* The rowsPerBank is determined based on the capacity, number of
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* ranks and banks, the burst size, and the row buffer size.
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*/
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uint32_t readBufferSize;
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uint32_t writeBufferSize;
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uint32_t writeHighThreshold;
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uint32_t writeLowThreshold;
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const uint32_t minWritesPerSwitch;
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const uint32_t minReadsPerSwitch;
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/**
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* Memory controller configuration initialized based on parameter
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* values.
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*/
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enums::MemSched memSchedPolicy;
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/**
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* Pipeline latency of the controller frontend. The frontend
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* contribution is added to writes (that complete when they are in
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* the write buffer) and reads that are serviced the write buffer.
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*/
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const Tick frontendLatency;
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/**
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* Pipeline latency of the backend and PHY. Along with the
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* frontend contribution, this latency is added to reads serviced
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* by the memory.
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*/
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const Tick backendLatency;
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/**
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* Length of a command window, used to check
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* command bandwidth
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*/
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const Tick commandWindow;
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|
|
/**
|
|
* Till when must we wait before issuing next RD/WR burst?
|
|
*/
|
|
Tick nextBurstAt;
|
|
|
|
Tick prevArrival;
|
|
|
|
/**
|
|
* The soonest you have to start thinking about the next request
|
|
* is the longest access time that can occur before
|
|
* nextBurstAt. Assuming you need to precharge, open a new row,
|
|
* and access, it is tRP + tRCD + tCL.
|
|
*/
|
|
Tick nextReqTime;
|
|
|
|
struct CtrlStats : public statistics::Group
|
|
{
|
|
CtrlStats(MemCtrl &ctrl);
|
|
|
|
void regStats() override;
|
|
|
|
MemCtrl &ctrl;
|
|
|
|
// All statistics that the model needs to capture
|
|
statistics::Scalar readReqs;
|
|
statistics::Scalar writeReqs;
|
|
statistics::Scalar readBursts;
|
|
statistics::Scalar writeBursts;
|
|
statistics::Scalar servicedByWrQ;
|
|
statistics::Scalar mergedWrBursts;
|
|
statistics::Scalar neitherReadNorWriteReqs;
|
|
// Average queue lengths
|
|
statistics::Average avgRdQLen;
|
|
statistics::Average avgWrQLen;
|
|
|
|
statistics::Scalar numRdRetry;
|
|
statistics::Scalar numWrRetry;
|
|
statistics::Vector readPktSize;
|
|
statistics::Vector writePktSize;
|
|
statistics::Vector rdQLenPdf;
|
|
statistics::Vector wrQLenPdf;
|
|
statistics::Histogram rdPerTurnAround;
|
|
statistics::Histogram wrPerTurnAround;
|
|
|
|
statistics::Scalar bytesReadWrQ;
|
|
statistics::Scalar bytesReadSys;
|
|
statistics::Scalar bytesWrittenSys;
|
|
// Average bandwidth
|
|
statistics::Formula avgRdBWSys;
|
|
statistics::Formula avgWrBWSys;
|
|
|
|
statistics::Scalar totGap;
|
|
statistics::Formula avgGap;
|
|
|
|
// per-requestor bytes read and written to memory
|
|
statistics::Vector requestorReadBytes;
|
|
statistics::Vector requestorWriteBytes;
|
|
|
|
// per-requestor bytes read and written to memory rate
|
|
statistics::Formula requestorReadRate;
|
|
statistics::Formula requestorWriteRate;
|
|
|
|
// per-requestor read and write serviced memory accesses
|
|
statistics::Vector requestorReadAccesses;
|
|
statistics::Vector requestorWriteAccesses;
|
|
|
|
// per-requestor read and write total memory access latency
|
|
statistics::Vector requestorReadTotalLat;
|
|
statistics::Vector requestorWriteTotalLat;
|
|
|
|
// per-requestor raed and write average memory access latency
|
|
statistics::Formula requestorReadAvgLat;
|
|
statistics::Formula requestorWriteAvgLat;
|
|
};
|
|
|
|
CtrlStats stats;
|
|
|
|
/**
|
|
* Upstream caches need this packet until true is returned, so
|
|
* hold it for deletion until a subsequent call
|
|
*/
|
|
std::unique_ptr<Packet> pendingDelete;
|
|
|
|
/**
|
|
* Select either the read or write queue
|
|
*
|
|
* @param is_read The current burst is a read, select read queue
|
|
* @return a reference to the appropriate queue
|
|
*/
|
|
std::vector<MemPacketQueue>& selQueue(bool is_read)
|
|
{
|
|
return (is_read ? readQueue : writeQueue);
|
|
};
|
|
|
|
virtual bool respQEmpty()
|
|
{
|
|
return respQueue.empty();
|
|
}
|
|
|
|
/**
|
|
* Checks if the memory interface is already busy
|
|
*
|
|
* @param mem_intr memory interface to check
|
|
* @return a boolean indicating if memory is busy
|
|
*/
|
|
virtual bool memBusy(MemInterface* mem_intr);
|
|
|
|
/**
|
|
* Will access memory interface and select non-deterministic
|
|
* reads to issue
|
|
* @param mem_intr memory interface to use
|
|
*/
|
|
virtual void nonDetermReads(MemInterface* mem_intr);
|
|
|
|
/**
|
|
* Will check if all writes are for nvm interface
|
|
* and nvm's write resp queue is full. The generic mem_intr is
|
|
* used as the same function can be called for a dram interface,
|
|
* in which case dram functions will eventually return false
|
|
* @param mem_intr memory interface to use
|
|
* @return a boolean showing if nvm is blocked with writes
|
|
*/
|
|
virtual bool nvmWriteBlock(MemInterface* mem_intr);
|
|
|
|
/**
|
|
* Remove commands that have already issued from burstTicks
|
|
*/
|
|
virtual void pruneBurstTick();
|
|
|
|
public:
|
|
|
|
MemCtrl(const MemCtrlParams &p);
|
|
|
|
/**
|
|
* Ensure that all interfaced have drained commands
|
|
*
|
|
* @return bool flag, set once drain complete
|
|
*/
|
|
virtual bool allIntfDrained() const;
|
|
|
|
DrainState drain() override;
|
|
|
|
/**
|
|
* Check for command bus contention for single cycle command.
|
|
* If there is contention, shift command to next burst.
|
|
* Check verifies that the commands issued per burst is less
|
|
* than a defined max number, maxCommandsPerWindow.
|
|
* Therefore, contention per cycle is not verified and instead
|
|
* is done based on a burst window.
|
|
*
|
|
* @param cmd_tick Initial tick of command, to be verified
|
|
* @param max_cmds_per_burst Number of commands that can issue
|
|
* in a burst window
|
|
* @return tick for command issue without contention
|
|
*/
|
|
virtual Tick verifySingleCmd(Tick cmd_tick, Tick max_cmds_per_burst,
|
|
bool row_cmd);
|
|
|
|
/**
|
|
* Check for command bus contention for multi-cycle (2 currently)
|
|
* command. If there is contention, shift command(s) to next burst.
|
|
* Check verifies that the commands issued per burst is less
|
|
* than a defined max number, maxCommandsPerWindow.
|
|
* Therefore, contention per cycle is not verified and instead
|
|
* is done based on a burst window.
|
|
*
|
|
* @param cmd_tick Initial tick of command, to be verified
|
|
* @param max_multi_cmd_split Maximum delay between commands
|
|
* @param max_cmds_per_burst Number of commands that can issue
|
|
* in a burst window
|
|
* @return tick for command issue without contention
|
|
*/
|
|
virtual Tick verifyMultiCmd(Tick cmd_tick, Tick max_cmds_per_burst,
|
|
Tick max_multi_cmd_split = 0);
|
|
|
|
/**
|
|
* Is there a respondEvent scheduled?
|
|
*
|
|
* @return true if event is scheduled
|
|
*/
|
|
virtual bool respondEventScheduled(uint8_t pseudo_channel = 0) const
|
|
{
|
|
assert(pseudo_channel == 0);
|
|
return respondEvent.scheduled();
|
|
}
|
|
|
|
/**
|
|
* Is there a read/write burst Event scheduled?
|
|
*
|
|
* @return true if event is scheduled
|
|
*/
|
|
virtual bool requestEventScheduled(uint8_t pseudo_channel = 0) const
|
|
{
|
|
assert(pseudo_channel == 0);
|
|
return nextReqEvent.scheduled();
|
|
}
|
|
|
|
/**
|
|
* restart the controller
|
|
* This can be used by interfaces to restart the
|
|
* scheduler after maintainence commands complete
|
|
* @param Tick to schedule next event
|
|
* @param pseudo_channel pseudo channel number for which scheduler
|
|
* needs to restart, will always be 0 for controllers which control
|
|
* only a single channel
|
|
*/
|
|
virtual void restartScheduler(Tick tick, uint8_t pseudo_channel = 0)
|
|
{
|
|
assert(pseudo_channel == 0);
|
|
schedule(nextReqEvent, tick);
|
|
}
|
|
|
|
/**
|
|
* Check the current direction of the memory channel
|
|
*
|
|
* @param next_state Check either the current or next bus state
|
|
* @return True when bus is currently in a read state
|
|
*/
|
|
bool inReadBusState(bool next_state, const MemInterface* mem_intr) const;
|
|
|
|
/**
|
|
* Check the current direction of the memory channel
|
|
*
|
|
* @param next_state Check either the current or next bus state
|
|
* @return True when bus is currently in a write state
|
|
*/
|
|
bool inWriteBusState(bool next_state, const MemInterface* mem_intr) const;
|
|
|
|
Port &getPort(const std::string &if_name,
|
|
PortID idx=InvalidPortID) override;
|
|
|
|
virtual void init() override;
|
|
virtual void startup() override;
|
|
virtual void drainResume() override;
|
|
|
|
protected:
|
|
|
|
virtual Tick recvAtomic(PacketPtr pkt);
|
|
virtual Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor);
|
|
virtual void recvFunctional(PacketPtr pkt);
|
|
virtual void recvMemBackdoorReq(const MemBackdoorReq &req,
|
|
MemBackdoorPtr &backdoor);
|
|
virtual bool recvTimingReq(PacketPtr pkt);
|
|
|
|
bool recvFunctionalLogic(PacketPtr pkt, MemInterface* mem_intr);
|
|
Tick recvAtomicLogic(PacketPtr pkt, MemInterface* mem_intr);
|
|
|
|
};
|
|
|
|
} // namespace memory
|
|
} // namespace gem5
|
|
|
|
#endif //__MEM_CTRL_HH__
|