524 lines
18 KiB
C++
524 lines
18 KiB
C++
/*
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* Copyright (c) 2010-2012,2017-2019 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mem/abstract_mem.hh"
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#include <vector>
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#include "base/loader/memory_image.hh"
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#include "base/loader/object_file.hh"
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#include "cpu/thread_context.hh"
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#include "debug/LLSC.hh"
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#include "debug/MemoryAccess.hh"
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#include "mem/packet_access.hh"
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#include "sim/system.hh"
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namespace gem5
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{
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namespace memory
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{
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AbstractMemory::AbstractMemory(const Params &p) :
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ClockedObject(p), range(p.range), pmemAddr(NULL),
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backdoor(params().range, nullptr,
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(MemBackdoor::Flags)(p.writeable ?
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MemBackdoor::Readable | MemBackdoor::Writeable :
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MemBackdoor::Readable)),
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confTableReported(p.conf_table_reported), inAddrMap(p.in_addr_map),
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kvmMap(p.kvm_map), writeable(p.writeable), collectStats(p.collect_stats),
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_system(NULL), stats(*this)
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{
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panic_if(!range.valid() || !range.size(),
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"Memory range %s must be valid with non-zero size.",
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range.to_string());
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}
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void
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AbstractMemory::initState()
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{
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ClockedObject::initState();
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const auto &file = params().image_file;
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if (file == "")
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return;
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auto *object = loader::createObjectFile(file, true);
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fatal_if(!object, "%s: Could not load %s.", name(), file);
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loader::debugSymbolTable.insert(*object->symtab().globals());
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loader::MemoryImage image = object->buildImage();
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AddrRange image_range(image.minAddr(), image.maxAddr());
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if (!range.contains(image_range.start())) {
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warn("%s: Moving image from %s to memory address range %s.",
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name(), image_range.to_string(), range.to_string());
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image = image.offset(range.start());
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image_range = AddrRange(image.minAddr(), image.maxAddr());
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}
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panic_if(!image_range.isSubset(range), "%s: memory image %s doesn't fit.",
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name(), file);
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PortProxy proxy([this](PacketPtr pkt) { functionalAccess(pkt); },
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system()->cacheLineSize());
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panic_if(!image.write(proxy), "%s: Unable to write image.");
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}
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void
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AbstractMemory::setBackingStore(uint8_t* pmem_addr)
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{
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// If there was an existing backdoor, let everybody know it's going away.
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if (backdoor.ptr())
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backdoor.invalidate();
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// The back door can't handle interleaved memory.
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backdoor.ptr(range.interleaved() ? nullptr : pmem_addr);
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pmemAddr = pmem_addr;
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}
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AbstractMemory::MemStats::MemStats(AbstractMemory &_mem)
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: statistics::Group(&_mem), mem(_mem),
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ADD_STAT(bytesRead, statistics::units::Byte::get(),
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"Number of bytes read from this memory"),
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ADD_STAT(bytesInstRead, statistics::units::Byte::get(),
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"Number of instructions bytes read from this memory"),
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ADD_STAT(bytesWritten, statistics::units::Byte::get(),
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"Number of bytes written to this memory"),
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ADD_STAT(numReads, statistics::units::Count::get(),
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"Number of read requests responded to by this memory"),
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ADD_STAT(numWrites, statistics::units::Count::get(),
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"Number of write requests responded to by this memory"),
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ADD_STAT(numOther, statistics::units::Count::get(),
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"Number of other requests responded to by this memory"),
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ADD_STAT(bwRead, statistics::units::Rate<
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statistics::units::Byte, statistics::units::Second>::get(),
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"Total read bandwidth from this memory"),
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ADD_STAT(bwInstRead,
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statistics::units::Rate<
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statistics::units::Byte, statistics::units::Second>::get(),
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"Instruction read bandwidth from this memory"),
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ADD_STAT(bwWrite, statistics::units::Rate<
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statistics::units::Byte, statistics::units::Second>::get(),
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"Write bandwidth from this memory"),
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ADD_STAT(bwTotal, statistics::units::Rate<
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statistics::units::Byte, statistics::units::Second>::get(),
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"Total bandwidth to/from this memory")
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{
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}
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void
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AbstractMemory::MemStats::regStats()
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{
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using namespace statistics;
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statistics::Group::regStats();
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System *sys = mem.system();
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assert(sys);
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const auto max_requestors = sys->maxRequestors();
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bytesRead
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.init(max_requestors)
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < max_requestors; i++) {
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bytesRead.subname(i, sys->getRequestorName(i));
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}
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bytesInstRead
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.init(max_requestors)
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < max_requestors; i++) {
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bytesInstRead.subname(i, sys->getRequestorName(i));
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}
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bytesWritten
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.init(max_requestors)
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < max_requestors; i++) {
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bytesWritten.subname(i, sys->getRequestorName(i));
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}
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numReads
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.init(max_requestors)
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < max_requestors; i++) {
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numReads.subname(i, sys->getRequestorName(i));
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}
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numWrites
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.init(max_requestors)
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < max_requestors; i++) {
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numWrites.subname(i, sys->getRequestorName(i));
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}
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numOther
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.init(max_requestors)
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < max_requestors; i++) {
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numOther.subname(i, sys->getRequestorName(i));
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}
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bwRead
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.precision(0)
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.prereq(bytesRead)
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < max_requestors; i++) {
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bwRead.subname(i, sys->getRequestorName(i));
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}
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bwInstRead
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.precision(0)
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.prereq(bytesInstRead)
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < max_requestors; i++) {
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bwInstRead.subname(i, sys->getRequestorName(i));
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}
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bwWrite
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.precision(0)
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.prereq(bytesWritten)
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < max_requestors; i++) {
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bwWrite.subname(i, sys->getRequestorName(i));
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}
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bwTotal
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.precision(0)
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.prereq(bwTotal)
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.flags(total | nozero | nonan)
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;
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for (int i = 0; i < max_requestors; i++) {
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bwTotal.subname(i, sys->getRequestorName(i));
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}
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bwRead = bytesRead / simSeconds;
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bwInstRead = bytesInstRead / simSeconds;
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bwWrite = bytesWritten / simSeconds;
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bwTotal = (bytesRead + bytesWritten) / simSeconds;
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}
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AddrRange
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AbstractMemory::getAddrRange() const
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{
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return range;
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}
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// Add load-locked to tracking list. Should only be called if the
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// operation is a load and the LLSC flag is set.
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void
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AbstractMemory::trackLoadLocked(PacketPtr pkt)
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{
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const RequestPtr &req = pkt->req;
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Addr paddr = LockedAddr::mask(req->getPaddr());
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// first we check if we already have a locked addr for this
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// xc. Since each xc only gets one, we just update the
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// existing record with the new address.
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std::list<LockedAddr>::iterator i;
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for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
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if (i->matchesContext(req)) {
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DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n",
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req->contextId(), paddr);
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i->addr = paddr;
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return;
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}
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}
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// no record for this xc: need to allocate a new one
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DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n",
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req->contextId(), paddr);
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lockedAddrList.push_front(LockedAddr(req));
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backdoor.invalidate();
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}
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// Called on *writes* only... both regular stores and
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// store-conditional operations. Check for conventional stores which
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// conflict with locked addresses, and for success/failure of store
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// conditionals.
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bool
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AbstractMemory::checkLockedAddrList(PacketPtr pkt)
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{
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const RequestPtr &req = pkt->req;
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Addr paddr = LockedAddr::mask(req->getPaddr());
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bool isLLSC = pkt->isLLSC();
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// Initialize return value. Non-conditional stores always
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// succeed. Assume conditional stores will fail until proven
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// otherwise.
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bool allowStore = !isLLSC;
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// Iterate over list. Note that there could be multiple matching records,
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// as more than one context could have done a load locked to this location.
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// Only remove records when we succeed in finding a record for (xc, addr);
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// then, remove all records with this address. Failed store-conditionals do
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// not blow unrelated reservations.
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std::list<LockedAddr>::iterator i = lockedAddrList.begin();
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if (isLLSC) {
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while (i != lockedAddrList.end()) {
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if (i->addr == paddr && i->matchesContext(req)) {
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// it's a store conditional, and as far as the memory system can
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// tell, the requesting context's lock is still valid.
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DPRINTF(LLSC, "StCond success: context %d addr %#x\n",
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req->contextId(), paddr);
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allowStore = true;
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break;
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}
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// If we didn't find a match, keep searching! Someone else may well
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// have a reservation on this line here but we may find ours in just
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// a little while.
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i++;
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}
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req->setExtraData(allowStore ? 1 : 0);
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}
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// LLSCs that succeeded AND non-LLSC stores both fall into here:
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if (allowStore) {
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// We write address paddr. However, there may be several entries with a
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// reservation on this address (for other contextIds) and they must all
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// be removed.
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i = lockedAddrList.begin();
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while (i != lockedAddrList.end()) {
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if (i->addr == paddr) {
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DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
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i->contextId, paddr);
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ContextID owner_cid = i->contextId;
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assert(owner_cid != InvalidContextID);
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ContextID requestor_cid = req->hasContextId() ?
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req->contextId() :
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InvalidContextID;
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if (owner_cid != requestor_cid) {
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ThreadContext* ctx = system()->threads[owner_cid];
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ctx->getIsaPtr()->globalClearExclusive();
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}
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i = lockedAddrList.erase(i);
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} else {
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i++;
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}
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}
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}
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return allowStore;
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}
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#if TRACING_ON
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static inline void
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tracePacket(System *sys, const char *label, PacketPtr pkt)
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{
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int size = pkt->getSize();
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if (size == 1 || size == 2 || size == 4 || size == 8) {
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ByteOrder byte_order = sys->getGuestByteOrder();
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DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x data "
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"%#x %c\n", label, sys->getRequestorName(pkt->req->
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requestorId()), size, pkt->getAddr(),
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pkt->getUintX(byte_order),
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pkt->req->isUncacheable() ? 'U' : 'C');
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return;
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}
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DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x %c\n",
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label, sys->getRequestorName(pkt->req->requestorId()),
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size, pkt->getAddr(), pkt->req->isUncacheable() ? 'U' : 'C');
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DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize());
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}
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# define TRACE_PACKET(A) tracePacket(system(), A, pkt)
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#else
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# define TRACE_PACKET(A)
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#endif
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void
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AbstractMemory::access(PacketPtr pkt)
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{
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if (pkt->cacheResponding()) {
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DPRINTF(MemoryAccess, "Cache responding to %#llx: not responding\n",
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pkt->getAddr());
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return;
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}
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if (pkt->cmd == MemCmd::CleanEvict || pkt->cmd == MemCmd::WritebackClean) {
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DPRINTF(MemoryAccess, "CleanEvict on 0x%x: not responding\n",
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pkt->getAddr());
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return;
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}
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assert(pkt->getAddrRange().isSubset(range));
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uint8_t *host_addr = toHostAddr(pkt->getAddr());
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if (pkt->cmd == MemCmd::SwapReq) {
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if (pkt->isAtomicOp()) {
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if (pmemAddr) {
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pkt->setData(host_addr);
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(*(pkt->getAtomicOp()))(host_addr);
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}
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} else {
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std::vector<uint8_t> overwrite_val(pkt->getSize());
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uint64_t condition_val64;
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uint32_t condition_val32;
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panic_if(!pmemAddr, "Swap only works if there is real memory " \
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"(i.e. null=False)");
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bool overwrite_mem = true;
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// keep a copy of our possible write value, and copy what is at the
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// memory address into the packet
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pkt->writeData(&overwrite_val[0]);
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pkt->setData(host_addr);
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if (pkt->req->isCondSwap()) {
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if (pkt->getSize() == sizeof(uint64_t)) {
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condition_val64 = pkt->req->getExtraData();
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overwrite_mem = !std::memcmp(&condition_val64, host_addr,
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sizeof(uint64_t));
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} else if (pkt->getSize() == sizeof(uint32_t)) {
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condition_val32 = (uint32_t)pkt->req->getExtraData();
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overwrite_mem = !std::memcmp(&condition_val32, host_addr,
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sizeof(uint32_t));
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} else
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panic("Invalid size for conditional read/write\n");
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}
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if (overwrite_mem)
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std::memcpy(host_addr, &overwrite_val[0], pkt->getSize());
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assert(!pkt->req->isInstFetch());
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TRACE_PACKET("Read/Write");
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if (collectStats) {
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stats.numOther[pkt->req->requestorId()]++;
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}
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}
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} else if (pkt->isRead()) {
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assert(!pkt->isWrite());
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if (pkt->isLLSC()) {
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assert(!pkt->fromCache());
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// if the packet is not coming from a cache then we have
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// to do the LL/SC tracking here
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trackLoadLocked(pkt);
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}
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if (pmemAddr) {
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pkt->setData(host_addr);
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}
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TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
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if (collectStats) {
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stats.numReads[pkt->req->requestorId()]++;
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stats.bytesRead[pkt->req->requestorId()] += pkt->getSize();
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if (pkt->req->isInstFetch()) {
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stats.bytesInstRead[pkt->req->requestorId()] += pkt->getSize();
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}
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}
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} else if (pkt->isInvalidate() || pkt->isClean()) {
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assert(!pkt->isWrite());
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// in a fastmem system invalidating and/or cleaning packets
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// can be seen due to cache maintenance requests
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// no need to do anything
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} else if (pkt->isWrite()) {
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if (writeOK(pkt)) {
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if (pmemAddr) {
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pkt->writeData(host_addr);
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DPRINTF(MemoryAccess, "%s write due to %s\n",
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__func__, pkt->print());
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}
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assert(!pkt->req->isInstFetch());
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TRACE_PACKET("Write");
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if (collectStats) {
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stats.numWrites[pkt->req->requestorId()]++;
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stats.bytesWritten[pkt->req->requestorId()] += pkt->getSize();
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}
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}
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} else {
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panic("Unexpected packet %s", pkt->print());
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}
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if (pkt->needsResponse()) {
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pkt->makeResponse();
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}
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}
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void
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AbstractMemory::functionalAccess(PacketPtr pkt)
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{
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assert(pkt->getAddrRange().isSubset(range));
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uint8_t *host_addr = toHostAddr(pkt->getAddr());
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if (pkt->isRead()) {
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if (pmemAddr) {
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pkt->setData(host_addr);
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}
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TRACE_PACKET("Read");
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pkt->makeResponse();
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} else if (pkt->isWrite()) {
|
|
if (pmemAddr) {
|
|
pkt->writeData(host_addr);
|
|
}
|
|
TRACE_PACKET("Write");
|
|
pkt->makeResponse();
|
|
} else if (pkt->isPrint()) {
|
|
Packet::PrintReqState *prs =
|
|
dynamic_cast<Packet::PrintReqState*>(pkt->senderState);
|
|
assert(prs);
|
|
// Need to call printLabels() explicitly since we're not going
|
|
// through printObj().
|
|
prs->printLabels();
|
|
// Right now we just print the single byte at the specified address.
|
|
ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *host_addr);
|
|
} else {
|
|
panic("AbstractMemory: unimplemented functional command %s",
|
|
pkt->cmdString());
|
|
}
|
|
}
|
|
|
|
} // namespace memory
|
|
} // namespace gem5
|