190c47270e
The way these were set up, there would be a conflict between SimObject files with the same name set up for different ISAs. This change creates a single file which tries to determine how many ISAs are enabled, and if there is exactly one, it creates a backwards compatible alias for the ISA specific CPU types. Change-Id: Iab358c2880d49222e814a98354c81d0f306fe1fc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52493 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabe.black@gmail.com> Reviewed-by: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
59 lines
2.7 KiB
Python
59 lines
2.7 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2004-2006 The Regents of The University of Michigan
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# Copyright (c) 2020 LabWare
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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Import('*')
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Source('decoder.cc', tags='mips isa')
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Source('dsp.cc', tags='mips isa')
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Source('faults.cc', tags='mips isa')
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Source('idle_event.cc', tags='mips isa')
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Source('interrupts.cc', tags='mips isa')
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Source('isa.cc', tags='mips isa')
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Source('linux/se_workload.cc', tags='mips isa')
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Source('pagetable.cc', tags='mips isa')
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Source('process.cc', tags='mips isa')
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Source('remote_gdb.cc', tags='mips isa')
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Source('se_workload.cc', tags='mips isa')
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Source('tlb.cc', tags='mips isa')
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Source('utility.cc', tags='mips isa')
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SimObject('MipsDecoder.py', sim_objects=['MipsDecoder'], tags='mips isa')
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SimObject('MipsInterrupts.py', sim_objects=['MipsInterrupts'], tags='mips isa')
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SimObject('MipsISA.py', sim_objects=['MipsISA'], tags='mips isa')
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SimObject('MipsMMU.py', sim_objects=['MipsMMU'], tags='mips isa')
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SimObject('MipsSeWorkload.py', sim_objects=['MipsSEWorkload', 'MipsEmuLinux'],
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tags='mips isa')
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SimObject('MipsTLB.py', sim_objects=['MipsTLB'], tags='mips isa')
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SimObject('MipsCPU.py', sim_objects=[], tags='mips isa')
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DebugFlag('MipsPRA', tags='mips isa')
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ISADesc('isa/main.isa', tags='mips isa')
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