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1868c9fd7f9805e6f0a9cf3ceab958c8b36259b0
gem5/src
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Kevin Lim 1868c9fd7f Fix for fetch to use the icache's block size to generate proper access size.
--HG--
extra : convert_revision : 0f292233ac05b584f527c32f80e3ca3d40a6a2c1
2006-12-11 23:47:30 -05:00
..
arch
Add no-op versions of ivlb and ivle back in for backwards compatibility.
2006-11-24 12:32:33 -05:00
base
Make cache compression policy a runtime virtual thing
2006-12-02 22:22:58 -08:00
cpu
Fix for fetch to use the icache's block size to generate proper access size.
2006-12-11 23:47:30 -05:00
dev
fix endian issues with condition codes
2006-11-10 20:17:42 -05:00
doxygen
Fix up doxygen.
2006-08-14 19:25:07 -04:00
kern
Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha specific DepTag constants.
2006-11-09 21:30:48 -05:00
mem
Don't compress data on writebacks unless it's actually necessary.
2006-12-05 07:16:36 -08:00
python
Support better param conversions to/from numeric subclasses.
2006-12-02 22:24:52 -08:00
sim
implement RUSAGE_CHILDREN for getrusage since it's trivial
2006-11-16 13:08:29 -08:00
unittest
Merge iceaxe.:/Volumes/work/research/m5/head
2006-06-11 22:01:34 -04:00
Doxyfile
Fix up doxygen.
2006-08-14 19:25:07 -04:00
SConscript
Turn cache MissQueue/BlockingBuffer into virtual object
2006-12-04 09:10:53 -08:00
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