16c1986fe2
Previously we use attribute and event for communication between gem5 SimObject to systemC fastmodel sc_module. Creating a base class allows us to perform casting once and get all the interface required. Also, instead of warning on attribute not found, we should make simulator panic if the sc_module does not provide the interface we need. Change-Id: I91e1036cb792d556dfc4010e7a0f138b1519b079 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40277 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
135 lines
4.4 KiB
C++
135 lines
4.4 KiB
C++
/*
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* Copyright 2019 Google, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ARM_FASTMODEL_IRIS_CPU_HH__
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#define __ARCH_ARM_FASTMODEL_IRIS_CPU_HH__
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#include "cpu/base.hh"
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#include "iris/detail/IrisInterface.h"
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#include "params/IrisBaseCPU.hh"
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#include "systemc/ext/core/sc_attr.hh"
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#include "systemc/ext/core/sc_event.hh"
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#include "systemc/ext/core/sc_module.hh"
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namespace Iris
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{
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// The base interface of the EVS used by gem5 BaseCPU below.
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class BaseCpuEvs
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{
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public:
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virtual void sendFunc(PacketPtr pkt) = 0;
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virtual void setClkPeriod(Tick clk_period) = 0;
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virtual void setCluster(SimObject *cluster) = 0;
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};
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// This CPU class adds some mechanisms which help attach the gem5 and fast
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// model CPUs to each other. It acts as a base class for the gem5 CPU, and
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// holds a pointer to the EVS. It also has some methods for setting up some
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// attributes in the fast model CPU to control its clock rate.
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class BaseCPU : public ::BaseCPU
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{
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public:
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BaseCPU(const BaseCPUParams ¶ms, sc_core::sc_module *_evs);
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virtual ~BaseCPU();
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Port &
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getDataPort() override
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{
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panic("%s not implemented.", __FUNCTION__);
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}
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Port &
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getInstPort() override
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{
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panic("%s not implemented.", __FUNCTION__);
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}
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void
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wakeup(ThreadID tid) override
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{
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auto *tc = threadContexts.at(tid);
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if (tc->status() == ::ThreadContext::Suspended)
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tc->activate();
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}
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Counter totalInsts() const override;
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Counter totalOps() const override { return totalInsts(); }
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PortProxy::SendFunctionalFunc
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getSendFunctional() override
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{
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return [this] (PacketPtr pkt) { evs_base_cpu->sendFunc(pkt); };
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}
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protected:
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sc_core::sc_module *evs;
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// Hold casted pointer to *evs.
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Iris::BaseCpuEvs *evs_base_cpu;
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protected:
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void
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clockPeriodUpdated() override
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{
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evs_base_cpu->setClkPeriod(clockPeriod());
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}
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void init() override;
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void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
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};
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// This class specializes the one above and sets up ThreadContexts based on
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// its template parameters. These ThreadContexts provide the standard gem5
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// interface and translate those accesses to use the Iris API to access that
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// state in the target context.
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template <class TC>
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class CPU : public Iris::BaseCPU
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{
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public:
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CPU(const IrisBaseCPUParams ¶ms,
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iris::IrisConnectionInterface *iris_if) :
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BaseCPU(params, params.evs)
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{
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const std::string parent_path = evs->name();
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System *sys = params.system;
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int thread_id = 0;
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for (const std::string &sub_path: params.thread_paths) {
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std::string path = parent_path + "." + sub_path;
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auto id = thread_id++;
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auto *tc = new TC(this, id, sys, params.mmu,
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params.isa[id], iris_if, path);
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threadContexts.push_back(tc);
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}
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}
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};
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} // namespace Iris
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#endif // __ARCH_ARM_FASTMODEL_IRIS_CPU_HH__
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