Files
gem5/src/arch/arm/fastmodel/iris/cpu.cc
Earl Ou 16c1986fe2 fastmodel: create base class for EVS CPU
Previously we use attribute and event for communication between gem5
SimObject to systemC fastmodel sc_module. Creating a base class allows us
to perform casting once and get all the interface required. Also,
instead of warning on attribute not found, we should make simulator
panic if the sc_module does not provide the interface we need.

Change-Id: I91e1036cb792d556dfc4010e7a0f138b1519b079
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40277
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-02 01:07:19 +00:00

81 lines
2.7 KiB
C++

/*
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#include "arch/arm/fastmodel/iris/cpu.hh"
#include "arch/arm/fastmodel/iris/thread_context.hh"
#include "scx/scx.h"
#include "sim/serialize.hh"
namespace Iris
{
BaseCPU::BaseCPU(const BaseCPUParams &params, sc_core::sc_module *_evs) :
::BaseCPU::BaseCPU(params), evs(_evs),
evs_base_cpu(dynamic_cast<Iris::BaseCpuEvs *>(_evs))
{
panic_if(!evs_base_cpu, "EVS should be of type BaseCpuEvs");
// Make sure fast model knows we're using debugging mechanisms to control
// the simulation, and it shouldn't shut down if simulation time stops
// for some reason. Despite the misleading name, this doesn't start a CADI
// server because it's first parameter is false.
scx::scx_start_cadi_server(false, false, true);
}
BaseCPU::~BaseCPU()
{
for (auto &tc: threadContexts)
delete tc;
threadContexts.clear();
}
Counter
BaseCPU::totalInsts() const
{
Counter count = 0;
for (auto *tc: threadContexts)
count += tc->getCurrentInstCount();
return count;
}
void
BaseCPU::init()
{
::BaseCPU::init();
for (auto *tc: threadContexts)
tc->initMemProxies(tc);
}
void
BaseCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
{
::serialize(*threadContexts[tid], cp);
}
} // namespace Iris