Steve Reinhardt 6677b9122a mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW ...

Makes x86-style locked operations even more distinct from
LLSC operations.  Using "locked" by itself should be
obviously ambiguous now.

2015-03-23 16:14:20 -07:00

..

alpha

arch: Make readMiscRegNoEffect const throughout

2015-02-16 03:33:28 -05:00

arm

arm: Share a port for the two table walker objects

2015-03-02 04:00:42 -05:00

generic

sim: Move the BaseTLB to src/arch/generic/

2015-02-11 10:23:27 -05:00

mips

arch: Make readMiscRegNoEffect const throughout

2015-02-16 03:33:28 -05:00

null

arch: Cleanup unused ISA traits constants

2014-09-03 07:42:21 -04:00

power

arch: Make readMiscRegNoEffect const throughout

2015-02-16 03:33:28 -05:00

sparc

arch: Make readMiscRegNoEffect const throughout

2015-02-16 03:33:28 -05:00

x86

mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW

2015-03-23 16:14:20 -07:00

isa_parser.py

arch: Allow named constants as decode case values.

2014-12-04 15:52:48 -08:00

micro_asm_test.py

Add a second section to make sure the ROM is extended properly.

2007-05-31 22:21:21 +00:00

micro_asm.py

scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access

2009-09-22 15:24:16 -07:00

SConscript

kvm, x86: Adding support for SE mode execution

2014-11-23 18:01:08 -08:00