ddf6cb88e4
This is reflect the updates made to black when running `pre-commit autoupdate`. Change-Id: Ifb7fea117f354c7f02f26926a5afdf7d67bc5919
85 lines
3.6 KiB
Python
85 lines
3.6 KiB
Python
# Copyright (c) 2023 Barcelona Supercomputing Center (BSC)
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# All rights reserved.
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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def upgrader(cpt):
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"""
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Update the checkpoint to support initial RVV implemtation.
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The updater is taking the following steps.
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1) Set vector registers to occupy 1280 bytes (40regs * 32bytes)
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2) Clear vector_element, vector_predicate and matrix registers
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3) Add RVV misc registers in the checkpoint
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"""
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for sec in cpt.sections():
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import re
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# Search for all XC sections
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if re.search(".*processor.*\.core.*\.xc.*", sec):
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# Updating RVV vector registers (dummy values)
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# Assuming VLEN = 256 bits (32 bytes)
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mr = cpt.get(sec, "regs.vector").split()
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if len(mr) <= 8:
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cpt.set(sec, "regs.vector", " ".join("0" for i in range(1280)))
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# Updating RVV vector element (dummy values)
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cpt.set(sec, "regs.vector_element", "")
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# Updating RVV vector predicate (dummy values)
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cpt.set(sec, "regs.vector_predicate", "")
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# Updating RVV matrix (dummy values)
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cpt.set(sec, "regs.matrix", "")
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# Search for all ISA sections
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if re.search(".*processor.*\.core.*\.isa$", sec):
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# Updating RVV misc registers (dummy values)
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mr = cpt.get(sec, "miscRegFile").split()
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if len(mr) == 164:
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print(
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"MISCREG_* RVV registers already seem " "to be inserted."
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)
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else:
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# Add dummy value for MISCREG_VSTART
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mr.insert(121, 0)
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# Add dummy value for MISCREG_VXSAT
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mr.insert(121, 0)
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# Add dummy value for MISCREG_VXRM
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mr.insert(121, 0)
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# Add dummy value for MISCREG_VCSR
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mr.insert(121, 0)
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# Add dummy value for MISCREG_VL
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mr.insert(121, 0)
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# Add dummy value for MISCREG_VTYPE
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mr.insert(121, 0)
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# Add dummy value for MISCREG_VLENB
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mr.insert(121, 0)
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cpt.set(sec, "miscRegFile", " ".join(str(x) for x in mr))
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legacy_version = 17
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