Andreas Hansson 14e5b2ea55 mem: Pass shared downstream through caches ...

This patch ensures that we pass on information about a packet being
shared (rather than exclusive), when forwarding a packet downstream.

Without this patch there is a risk that a downstream cache considers
the line exclusive when it really isn't.

2015-05-05 03:22:26 -04:00

..

cache

mem: Pass shared downstream through caches

2015-05-05 03:22:26 -04:00

protocol

ruby: interface with classic memory controller

2014-11-06 05:42:21 -06:00

ruby

ruby: set: replace long by unsigned long

2015-04-29 22:35:22 -05:00

slicc

ruby: interface with classic memory controller

2014-11-06 05:42:21 -06:00

abstract_mem.cc

mem: Support WriteInvalidate (again)

2014-12-02 06:08:19 -05:00

abstract_mem.hh

mem: Dynamically determine page bytes in memory components

2014-10-16 05:49:43 -04:00

AbstractMemory.py

mem: Change AbstractMemory defaults to match the common case

2013-08-19 03:52:33 -04:00

addr_mapper.cc

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

addr_mapper.hh

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

AddrMapper.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

bridge.cc

mem: Use emplace front/back for deferred packets

2015-03-19 04:06:11 -04:00

bridge.hh

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

Bridge.py

mem: Tidy up the bridge with const and additional checks

2013-06-27 05:49:49 -04:00

coherent_xbar.cc

mem: Add crossbar latencies

2015-03-02 04:00:46 -05:00

coherent_xbar.hh

mem: Add crossbar latencies

2015-03-02 04:00:46 -05:00

comm_monitor.cc

mem: Enable CommMonitor to output traces in atomic mode

2015-03-19 04:06:10 -04:00

comm_monitor.hh

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

CommMonitor.py

mem: Add stack distance statistics to the CommMonitor

2014-12-23 09:31:18 -05:00

dram_ctrl.cc

mem: Simplify page close checks for adaptive policies

2015-04-29 22:35:22 -05:00

dram_ctrl.hh

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

DRAMCtrl.py

config: Adjust DRAM channel interleaving defaults

2015-02-03 14:25:52 -05:00

drampower.cc

mem: Add a GDDR5 DRAM config

2014-12-02 06:07:32 -05:00

drampower.hh

mem: Add DRAMPower wrapping class

2014-07-29 17:29:36 +01:00

dramsim2_wrapper.cc

mem: Add a wrapped DRAMSim2 memory controller

2014-02-18 05:50:53 -05:00

dramsim2_wrapper.hh

mem: Add a wrapped DRAMSim2 memory controller

2014-02-18 05:50:53 -05:00

dramsim2.cc

mem: Downstream components consumes new crossbar delays

2015-03-02 04:00:48 -05:00

dramsim2.hh

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

DRAMSim2.py

mem: Add a wrapped DRAMSim2 memory controller

2014-02-18 05:50:53 -05:00

external_master.cc

mem: Add ExternalMaster and ExternalSlave ports

2014-10-16 05:49:56 -04:00

external_master.hh

mem: Add ExternalMaster and ExternalSlave ports

2014-10-16 05:49:56 -04:00

external_slave.cc

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

external_slave.hh

mem: Add ExternalMaster and ExternalSlave ports

2014-10-16 05:49:56 -04:00

ExternalMaster.py

mem: Add ExternalMaster and ExternalSlave ports

2014-10-16 05:49:56 -04:00

ExternalSlave.py

mem: Add ExternalMaster and ExternalSlave ports

2014-10-16 05:49:56 -04:00

fs_translating_port_proxy.cc

mem: Use const pointers for port proxy write functions

2014-12-02 06:07:38 -05:00

fs_translating_port_proxy.hh

mem: Use const pointers for port proxy write functions

2014-12-02 06:07:38 -05:00

mem_checker_monitor.cc

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

mem_checker_monitor.hh

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

mem_checker.cc

mem: Fix initial value problem with MemChecker

2015-02-16 03:34:47 -05:00

mem_checker.hh

mem: Add MemChecker and MemCheckerMonitor

2014-12-23 09:31:17 -05:00

mem_object.cc

Port: Add protocol-agnostic ports in the port hierarchy

2012-10-15 08:12:35 -04:00

mem_object.hh

Port: Add protocol-agnostic ports in the port hierarchy

2012-10-15 08:12:35 -04:00

MemChecker.py

mem: Add MemChecker and MemCheckerMonitor

2014-12-23 09:31:17 -05:00

MemObject.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

mport.cc

MEM: Separate snoops and normal memory requests/responses

2012-04-14 05:45:07 -04:00

mport.hh

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

multi_level_page_table_impl.hh

mem: Page Table map api modification

2014-11-23 18:01:09 -08:00

multi_level_page_table.cc

mem: adding a multi-level page table class

2014-04-01 12:18:12 -05:00

multi_level_page_table.hh

mem: Page Table map api modification

2014-11-23 18:01:09 -08:00

noncoherent_xbar.cc

mem: Add crossbar latencies

2015-03-02 04:00:46 -05:00

noncoherent_xbar.hh

mem: Add crossbar latencies

2015-03-02 04:00:46 -05:00

packet_access.hh

mem: Add const getters for write packet data

2014-12-02 06:07:36 -05:00

packet_queue.cc

mem: Use emplace front/back for deferred packets

2015-03-19 04:06:11 -04:00

packet_queue.hh

mem: Add option to force in-order insertion in PacketQueue

2015-03-02 04:00:49 -05:00

packet.cc

mem: Add byte mask to Packet::checkFunctional

2015-03-02 04:00:52 -05:00

packet.hh

mem: Rename PREFETCH_SNOOP_SQUASH flag to BLOCK_CACHED

2015-03-27 04:55:54 -04:00

page_table.cc

mem: Page Table map api modification

2014-11-23 18:01:09 -08:00

page_table.hh

mem: Page Table map api modification

2014-11-23 18:01:09 -08:00

physical.cc

mem: mmap the backing store with MAP_NORESERVE

2015-02-16 03:33:47 -05:00

physical.hh

mem: mmap the backing store with MAP_NORESERVE

2015-02-16 03:33:47 -05:00

port_proxy.cc

mem: Clean up Request initialisation

2015-01-22 05:00:53 -05:00

port_proxy.hh

mem: Use const pointers for port proxy write functions

2014-12-02 06:07:38 -05:00

port.cc

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

port.hh

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

qport.hh

mem: Add option to force in-order insertion in PacketQueue

2015-03-02 04:00:49 -05:00

request.hh

mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW

2015-03-23 16:14:20 -07:00

SConscript

mem: Add a stack distance calculator

2014-12-23 09:31:18 -05:00

se_translating_port_proxy.cc

mem: Use const pointers for port proxy write functions

2014-12-02 06:07:38 -05:00

se_translating_port_proxy.hh

mem: Use const pointers for port proxy write functions

2014-12-02 06:07:38 -05:00

simple_mem.cc

mem: Use emplace front/back for deferred packets

2015-03-19 04:06:11 -04:00

simple_mem.hh

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

SimpleMemory.py

mem: Add an internal packet queue in SimpleMemory

2013-08-19 03:52:25 -04:00

snoop_filter.cc

mem: Add access statistics for the snoop filter

2014-04-25 12:36:16 +01:00

snoop_filter.hh

mem: Add access statistics for the snoop filter

2014-04-25 12:36:16 +01:00

stack_dist_calc.cc

mem: Add a stack distance calculator

2014-12-23 09:31:18 -05:00

stack_dist_calc.hh

mem: Add a stack distance calculator

2014-12-23 09:31:18 -05:00

StackDistCalc.py

mem: Add a stack distance calculator

2014-12-23 09:31:18 -05:00

tport.cc

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

tport.hh

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

xbar.cc

mem: Add crossbar latencies

2015-03-02 04:00:46 -05:00

xbar.hh

mem: Add crossbar latencies

2015-03-02 04:00:46 -05:00

XBar.py

mem: Move crossbar default latencies to subclasses

2015-03-02 04:00:47 -05:00