60e4ad955d
Encapsulate all ruby-related files in a ruby namespace. Change-Id: If642c9751ecefc35b45c5dd69d85e67813cc5224 Issued-on: https://gem5.atlassian.net/browse/GEM5-984 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47307 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
335 lines
12 KiB
C++
335 lines
12 KiB
C++
/*
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* Copyright (c) 2019-2021 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
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#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
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#include <iostream>
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#include <list>
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#include <unordered_map>
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/protocol/MachineType.hh"
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#include "mem/ruby/protocol/RubyRequestType.hh"
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#include "mem/ruby/protocol/SequencerRequestType.hh"
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#include "mem/ruby/structures/CacheMemory.hh"
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#include "mem/ruby/system/RubyPort.hh"
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#include "params/RubySequencer.hh"
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namespace gem5
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{
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namespace ruby
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{
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struct SequencerRequest
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{
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PacketPtr pkt;
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RubyRequestType m_type;
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RubyRequestType m_second_type;
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Cycles issue_time;
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SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type,
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RubyRequestType _m_second_type, Cycles _issue_time)
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: pkt(_pkt), m_type(_m_type), m_second_type(_m_second_type),
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issue_time(_issue_time)
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{}
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bool functionalWrite(Packet *func_pkt) const
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{
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// Follow-up on RubyRequest::functionalWrite
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// This makes sure the hitCallback won't overrite the value we
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// expect to find
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assert(func_pkt->isWrite());
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return func_pkt->trySatisfyFunctional(pkt);
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}
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};
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std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
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class Sequencer : public RubyPort
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{
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public:
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typedef RubySequencerParams Params;
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Sequencer(const Params &);
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~Sequencer();
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/**
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* Proxy function to writeCallback that first
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* invalidates the line address in the local monitor.
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*/
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void writeCallbackScFail(Addr address,
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DataBlock& data);
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// Public Methods
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virtual void wakeup(); // Used only for deadlock detection
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void resetStats() override;
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void collateStats();
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void writeCallback(Addr address,
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DataBlock& data,
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const bool externalHit = false,
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const MachineType mach = MachineType_NUM,
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const Cycles initialRequestTime = Cycles(0),
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const Cycles forwardRequestTime = Cycles(0),
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const Cycles firstResponseTime = Cycles(0),
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const bool noCoales = false);
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// Write callback that prevents coalescing
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void writeUniqueCallback(Addr address, DataBlock& data)
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{
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writeCallback(address, data, true, MachineType_NUM, Cycles(0),
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Cycles(0), Cycles(0), true);
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}
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void readCallback(Addr address,
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DataBlock& data,
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const bool externalHit = false,
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const MachineType mach = MachineType_NUM,
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const Cycles initialRequestTime = Cycles(0),
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const Cycles forwardRequestTime = Cycles(0),
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const Cycles firstResponseTime = Cycles(0));
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RequestStatus makeRequest(PacketPtr pkt) override;
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virtual bool empty() const;
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int outstandingCount() const override { return m_outstanding_count; }
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bool isDeadlockEventScheduled() const override
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{ return deadlockCheckEvent.scheduled(); }
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void descheduleDeadlockEvent() override
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{ deschedule(deadlockCheckEvent); }
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virtual void print(std::ostream& out) const;
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void markRemoved();
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void evictionCallback(Addr address);
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int coreId() const { return m_coreId; }
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virtual int functionalWrite(Packet *func_pkt) override;
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void recordRequestType(SequencerRequestType requestType);
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statistics::Histogram& getOutstandReqHist() { return m_outstandReqHist; }
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statistics::Histogram& getLatencyHist() { return m_latencyHist; }
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statistics::Histogram& getTypeLatencyHist(uint32_t t)
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{ return *m_typeLatencyHist[t]; }
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statistics::Histogram& getHitLatencyHist() { return m_hitLatencyHist; }
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statistics::Histogram& getHitTypeLatencyHist(uint32_t t)
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{ return *m_hitTypeLatencyHist[t]; }
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statistics::Histogram& getHitMachLatencyHist(uint32_t t)
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{ return *m_hitMachLatencyHist[t]; }
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statistics::Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t)
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{ return *m_hitTypeMachLatencyHist[r][t]; }
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statistics::Histogram& getMissLatencyHist()
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{ return m_missLatencyHist; }
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statistics::Histogram& getMissTypeLatencyHist(uint32_t t)
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{ return *m_missTypeLatencyHist[t]; }
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statistics::Histogram& getMissMachLatencyHist(uint32_t t) const
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{ return *m_missMachLatencyHist[t]; }
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statistics::Histogram&
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getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
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{ return *m_missTypeMachLatencyHist[r][t]; }
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statistics::Histogram& getIssueToInitialDelayHist(uint32_t t) const
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{ return *m_IssueToInitialDelayHist[t]; }
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statistics::Histogram&
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getInitialToForwardDelayHist(const MachineType t) const
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{ return *m_InitialToForwardDelayHist[t]; }
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statistics::Histogram&
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getForwardRequestToFirstResponseHist(const MachineType t) const
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{ return *m_ForwardToFirstResponseDelayHist[t]; }
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statistics::Histogram&
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getFirstResponseToCompletionDelayHist(const MachineType t) const
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{ return *m_FirstResponseToCompletionDelayHist[t]; }
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statistics::Counter getIncompleteTimes(const MachineType t) const
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{ return m_IncompleteTimes[t]; }
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private:
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void issueRequest(PacketPtr pkt, RubyRequestType type);
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void hitCallback(SequencerRequest* srequest, DataBlock& data,
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bool llscSuccess,
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const MachineType mach, const bool externalHit,
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const Cycles initialRequestTime,
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const Cycles forwardRequestTime,
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const Cycles firstResponseTime,
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const bool was_coalesced);
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void recordMissLatency(SequencerRequest* srequest, bool llscSuccess,
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const MachineType respondingMach,
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bool isExternalHit, Cycles initialRequestTime,
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Cycles forwardRequestTime,
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Cycles firstResponseTime);
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// Private copy constructor and assignment operator
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Sequencer(const Sequencer& obj);
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Sequencer& operator=(const Sequencer& obj);
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protected:
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// RequestTable contains both read and write requests, handles aliasing
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std::unordered_map<Addr, std::list<SequencerRequest>> m_RequestTable;
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Cycles m_deadlock_threshold;
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virtual RequestStatus insertRequest(PacketPtr pkt,
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RubyRequestType primary_type,
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RubyRequestType secondary_type);
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private:
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int m_max_outstanding_requests;
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CacheMemory* m_dataCache_ptr;
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// The cache access latency for top-level caches (L0/L1). These are
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// currently assessed at the beginning of each memory access through the
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// sequencer.
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// TODO: Migrate these latencies into top-level cache controllers.
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Cycles m_data_cache_hit_latency;
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Cycles m_inst_cache_hit_latency;
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// Global outstanding request count, across all request tables
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int m_outstanding_count;
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bool m_deadlock_check_scheduled;
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int m_coreId;
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bool m_runningGarnetStandalone;
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//! Histogram for number of outstanding requests per cycle.
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statistics::Histogram m_outstandReqHist;
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//! Histogram for holding latency profile of all requests.
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statistics::Histogram m_latencyHist;
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std::vector<statistics::Histogram *> m_typeLatencyHist;
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//! Histogram for holding latency profile of all requests that
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//! hit in the controller connected to this sequencer.
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statistics::Histogram m_hitLatencyHist;
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std::vector<statistics::Histogram *> m_hitTypeLatencyHist;
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//! Histograms for profiling the latencies for requests that
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//! did not required external messages.
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std::vector<statistics::Histogram *> m_hitMachLatencyHist;
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std::vector<std::vector<statistics::Histogram *>> m_hitTypeMachLatencyHist;
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//! Histogram for holding latency profile of all requests that
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//! miss in the controller connected to this sequencer.
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statistics::Histogram m_missLatencyHist;
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std::vector<statistics::Histogram *> m_missTypeLatencyHist;
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//! Histograms for profiling the latencies for requests that
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//! required external messages.
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std::vector<statistics::Histogram *> m_missMachLatencyHist;
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std::vector<std::vector<statistics::Histogram *>>
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m_missTypeMachLatencyHist;
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//! Histograms for recording the breakdown of miss latency
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std::vector<statistics::Histogram *> m_IssueToInitialDelayHist;
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std::vector<statistics::Histogram *> m_InitialToForwardDelayHist;
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std::vector<statistics::Histogram *> m_ForwardToFirstResponseDelayHist;
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std::vector<statistics::Histogram *> m_FirstResponseToCompletionDelayHist;
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std::vector<statistics::Counter> m_IncompleteTimes;
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EventFunctionWrapper deadlockCheckEvent;
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// support for LL/SC
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/**
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* Places the cache line address into the global monitor
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* tagged with this Sequencer object's version id.
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*/
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void llscLoadLinked(const Addr);
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/**
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* Removes the cache line address from the global monitor.
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* This is independent of this Sequencer object's version id.
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*/
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void llscClearMonitor(const Addr);
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/**
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* Searches for cache line address in the global monitor
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* tagged with this Sequencer object's version id.
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* If a match is found, the entry is is erased from
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* the global monitor.
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*
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* @return a boolean indicating if the line address was found.
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*/
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bool llscStoreConditional(const Addr);
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public:
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/**
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* Searches for cache line address in the global monitor
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* tagged with this Sequencer object's version id.
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*
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* @return a boolean indicating if the line address was found.
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*/
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bool llscCheckMonitor(const Addr);
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/**
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* Removes all addresses from the local monitor.
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* This is independent of this Sequencer object's version id.
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*/
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void llscClearLocalMonitor();
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};
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inline std::ostream&
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operator<<(std::ostream& out, const Sequencer& obj)
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{
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obj.print(out);
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out << std::flush;
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return out;
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}
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} // namespace ruby
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} // namespace gem5
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#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__
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