Ali Saidi 77bea2fb42 CPU: Add some useful debug message to the timing simple cpu.

2011-05-04 20:38:27 -05:00

..

atomic.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

atomic.hh

CPU: Add readBytes and writeBytes functions to the exec contexts.

2010-08-13 06:16:02 -07:00

AtomicSimpleCPU.py

Config: Keep track of uncached and cached ports separately.

2011-02-03 20:23:00 -08:00

base.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

base.hh

CPU: Fix a case where timing simple cpu faults can nest.

2011-05-04 20:38:27 -05:00

BaseSimpleCPU.py

params: Convert the CPU objects to use the auto generated param structs.

2008-08-11 12:22:16 -07:00

SConscript

params: Convert the CPU objects to use the auto generated param structs.

2008-08-11 12:22:16 -07:00

SConsopts

cpu_models: get rid of cpu_models.py and move the stuff into SCons

2010-02-26 18:14:48 -08:00

timing.cc

CPU: Add some useful debug message to the timing simple cpu.

2011-05-04 20:38:27 -05:00

timing.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

TimingSimpleCPU.py

Config: Keep track of uncached and cached ports separately.

2011-02-03 20:23:00 -08:00