7315bf685a
Change-Id: Idfd8e71856931fa101e00c58a2aa4018d6666076 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42093 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
1194 lines
39 KiB
C++
1194 lines
39 KiB
C++
/*
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* Copyright (c) 2011, 2013, 2016-2020 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* Copyright (c) 2009 The University of Edinburgh
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_BASE_DYN_INST_HH__
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#define __CPU_BASE_DYN_INST_HH__
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#include <algorithm>
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#include <array>
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#include <bitset>
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#include <deque>
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#include <list>
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#include <string>
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#include "arch/generic/tlb.hh"
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#include "arch/utility.hh"
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#include "base/trace.hh"
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#include "config/the_isa.hh"
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#include "cpu/checker/cpu.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/inst_res.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/op_class.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/translation.hh"
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#include "debug/HtmCpu.hh"
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#include "mem/packet.hh"
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#include "mem/request.hh"
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#include "sim/byteswap.hh"
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#include "sim/system.hh"
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/**
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* @file
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* Defines a dynamic instruction context.
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*/
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template <class Impl>
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class BaseDynInst : public ExecContext, public RefCounted
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{
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public:
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// Typedef for the CPU.
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typedef typename Impl::CPUType ImplCPU;
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typedef typename ImplCPU::ImplState ImplState;
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using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*;
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using LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator;
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using SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator;
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// The DynInstPtr type.
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
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// The list of instructions iterator type.
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typedef typename std::list<DynInstPtr>::iterator ListIt;
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protected:
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enum Status {
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IqEntry, /// Instruction is in the IQ
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RobEntry, /// Instruction is in the ROB
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LsqEntry, /// Instruction is in the LSQ
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Completed, /// Instruction has completed
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ResultReady, /// Instruction has its result
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CanIssue, /// Instruction can issue and execute
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Issued, /// Instruction has issued
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Executed, /// Instruction has executed
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CanCommit, /// Instruction can commit
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AtCommit, /// Instruction has reached commit
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Committed, /// Instruction has committed
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Squashed, /// Instruction is squashed
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SquashedInIQ, /// Instruction is squashed in the IQ
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SquashedInLSQ, /// Instruction is squashed in the LSQ
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SquashedInROB, /// Instruction is squashed in the ROB
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PinnedRegsRenamed, /// Pinned registers are renamed
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PinnedRegsWritten, /// Pinned registers are written back
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PinnedRegsSquashDone, /// Regs pinning status updated after squash
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RecoverInst, /// Is a recover instruction
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BlockingInst, /// Is a blocking instruction
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ThreadsyncWait, /// Is a thread synchronization instruction
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SerializeBefore, /// Needs to serialize on
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/// instructions ahead of it
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SerializeAfter, /// Needs to serialize instructions behind it
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SerializeHandled, /// Serialization has been handled
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NumStatus
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};
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enum Flags {
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NotAnInst,
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TranslationStarted,
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TranslationCompleted,
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PossibleLoadViolation,
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HitExternalSnoop,
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EffAddrValid,
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RecordResult,
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Predicate,
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MemAccPredicate,
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PredTaken,
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IsStrictlyOrdered,
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ReqMade,
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MemOpDone,
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HtmFromTransaction,
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MaxFlags
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};
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public:
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/** The sequence number of the instruction. */
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InstSeqNum seqNum;
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/** The StaticInst used by this BaseDynInst. */
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const StaticInstPtr staticInst;
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/** Pointer to the Impl's CPU object. */
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ImplCPU *cpu;
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BaseCPU *getCpuPtr() { return cpu; }
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/** Pointer to the thread state. */
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ImplState *thread;
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/** The kind of fault this instruction has generated. */
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Fault fault;
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/** InstRecord that tracks this instructions. */
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Trace::InstRecord *traceData;
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protected:
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/** The result of the instruction; assumes an instruction can have many
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* destination registers.
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*/
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std::queue<InstResult> instResult;
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/** PC state for this instruction. */
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TheISA::PCState pc;
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private:
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/* An amalgamation of a lot of boolean values into one */
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std::bitset<MaxFlags> instFlags;
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/** The status of this BaseDynInst. Several bits can be set. */
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std::bitset<NumStatus> status;
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protected:
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/**
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* Collect register related information into a single struct. The number of
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* source and destination registers can vary, and storage for information
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* about them needs to be allocated dynamically. This class figures out
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* how much space is needed and allocates it all at once, and then
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* trivially divies it up for each type of per-register array.
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*/
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struct Regs
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{
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private:
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size_t _numSrcs;
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size_t _numDests;
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size_t srcsReady = 0;
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using BackingStorePtr = std::unique_ptr<uint8_t[]>;
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using BufCursor = BackingStorePtr::pointer;
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BackingStorePtr buf;
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// Members should be ordered based on required alignment so that they
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// can be allocated contiguously.
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// Flattened register index of the destination registers of this
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// instruction.
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RegId *_flatDestIdx;
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// Physical register index of the destination registers of this
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// instruction.
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PhysRegIdPtr *_destIdx;
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// Physical register index of the previous producers of the
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// architected destinations.
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PhysRegIdPtr *_prevDestIdx;
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static inline size_t
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bytesForDests(size_t num)
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{
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return (sizeof(RegId) + 2 * sizeof(PhysRegIdPtr)) * num;
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}
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// Physical register index of the source registers of this instruction.
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PhysRegIdPtr *_srcIdx;
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// Whether or not the source register is ready, one bit per register.
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uint8_t *_readySrcIdx;
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static inline size_t
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bytesForSources(size_t num)
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{
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return sizeof(PhysRegIdPtr) * num +
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sizeof(uint8_t) * ((num + 7) / 8);
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}
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template <class T>
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static inline void
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allocate(T *&ptr, BufCursor &cur, size_t count)
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{
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ptr = new (cur) T[count];
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cur += sizeof(T) * count;
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}
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public:
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size_t numSrcs() const { return _numSrcs; }
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size_t numDests() const { return _numDests; }
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void
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init()
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{
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std::fill(_readySrcIdx, _readySrcIdx + (numSrcs() + 7) / 8, 0);
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}
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Regs(size_t srcs, size_t dests) : _numSrcs(srcs), _numDests(dests),
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buf(new uint8_t[bytesForSources(srcs) + bytesForDests(dests)])
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{
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BufCursor cur = buf.get();
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allocate(_flatDestIdx, cur, dests);
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allocate(_destIdx, cur, dests);
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allocate(_prevDestIdx, cur, dests);
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allocate(_srcIdx, cur, srcs);
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allocate(_readySrcIdx, cur, (srcs + 7) / 8);
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init();
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}
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// Returns the flattened register index of the idx'th destination
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// register.
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const RegId &
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flattenedDestIdx(int idx) const
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{
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return _flatDestIdx[idx];
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}
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// Flattens a destination architectural register index into a logical
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// index.
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void
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flattenedDestIdx(int idx, const RegId ®_id)
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{
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_flatDestIdx[idx] = reg_id;
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}
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// Returns the physical register index of the idx'th destination
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// register.
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PhysRegIdPtr
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renamedDestIdx(int idx) const
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{
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return _destIdx[idx];
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}
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// Set the renamed dest register id.
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void
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renamedDestIdx(int idx, PhysRegIdPtr phys_reg_id)
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{
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_destIdx[idx] = phys_reg_id;
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}
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// Returns the physical register index of the previous physical
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// register that remapped to the same logical register index.
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PhysRegIdPtr
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prevDestIdx(int idx) const
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{
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return _prevDestIdx[idx];
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}
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// Set the previous renamed dest register id.
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void
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prevDestIdx(int idx, PhysRegIdPtr phys_reg_id)
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{
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_prevDestIdx[idx] = phys_reg_id;
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}
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// Returns the physical register index of the i'th source register.
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PhysRegIdPtr
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renamedSrcIdx(int idx) const
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{
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return _srcIdx[idx];
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}
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void
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renamedSrcIdx(int idx, PhysRegIdPtr phys_reg_id)
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{
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_srcIdx[idx] = phys_reg_id;
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}
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bool
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readySrcIdx(int idx) const
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{
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uint8_t &byte = _readySrcIdx[idx / 8];
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return bits(byte, idx % 8);
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}
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void
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readySrcIdx(int idx, bool ready)
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{
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uint8_t &byte = _readySrcIdx[idx / 8];
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replaceBits(byte, idx % 8, ready ? 1 : 0);
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}
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};
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public:
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Regs regs;
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/** The thread this instruction is from. */
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ThreadID threadNumber;
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/** Iterator pointing to this BaseDynInst in the list of all insts. */
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ListIt instListIt;
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////////////////////// Branch Data ///////////////
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/** Predicted PC state after this instruction. */
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TheISA::PCState predPC;
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/** The Macroop if one exists */
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const StaticInstPtr macroop;
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/** How many source registers are ready. */
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uint8_t readyRegs;
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public:
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/////////////////////// Load Store Data //////////////////////
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/** The effective virtual address (lds & stores only). */
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Addr effAddr;
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/** The effective physical address. */
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Addr physEffAddr;
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/** The memory request flags (from translation). */
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unsigned memReqFlags;
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/** The size of the request */
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unsigned effSize;
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/** Pointer to the data for the memory access. */
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uint8_t *memData;
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/** Load queue index. */
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ssize_t lqIdx;
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LQIterator lqIt;
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/** Store queue index. */
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ssize_t sqIdx;
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SQIterator sqIt;
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/////////////////////// TLB Miss //////////////////////
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/**
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* Saved memory request (needed when the DTB address translation is
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* delayed due to a hw page table walk).
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*/
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LSQRequestPtr savedReq;
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/////////////////////// Checker //////////////////////
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// Need a copy of main request pointer to verify on writes.
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RequestPtr reqToVerify;
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private:
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// hardware transactional memory
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uint64_t htmUid;
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uint64_t htmDepth;
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public:
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/** Records changes to result? */
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void recordResult(bool f) { instFlags[RecordResult] = f; }
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/** Is the effective virtual address valid. */
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bool effAddrValid() const { return instFlags[EffAddrValid]; }
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void effAddrValid(bool b) { instFlags[EffAddrValid] = b; }
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/** Whether or not the memory operation is done. */
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bool memOpDone() const { return instFlags[MemOpDone]; }
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void memOpDone(bool f) { instFlags[MemOpDone] = f; }
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bool notAnInst() const { return instFlags[NotAnInst]; }
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void setNotAnInst() { instFlags[NotAnInst] = true; }
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////////////////////////////////////////////
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//
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// INSTRUCTION EXECUTION
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//
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////////////////////////////////////////////
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void
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demapPage(Addr vaddr, uint64_t asn) override
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{
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cpu->demapPage(vaddr, asn);
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}
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Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
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const std::vector<bool> &byte_enable) override;
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Fault initiateHtmCmd(Request::Flags flags) override;
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Fault writeMem(uint8_t *data, unsigned size, Addr addr,
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Request::Flags flags, uint64_t *res,
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const std::vector<bool> &byte_enable) override;
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Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
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AtomicOpFunctorPtr amo_op) override;
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/** True if the DTB address translation has started. */
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bool translationStarted() const { return instFlags[TranslationStarted]; }
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void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
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/** True if the DTB address translation has completed. */
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bool translationCompleted() const { return instFlags[TranslationCompleted]; }
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void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
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/** True if this address was found to match a previous load and they issued
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* out of order. If that happend, then it's only a problem if an incoming
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* snoop invalidate modifies the line, in which case we need to squash.
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* If nothing modified the line the order doesn't matter.
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*/
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bool
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possibleLoadViolation() const
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{
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return instFlags[PossibleLoadViolation];
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}
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void
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possibleLoadViolation(bool f)
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{
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instFlags[PossibleLoadViolation] = f;
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}
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/** True if the address hit a external snoop while sitting in the LSQ.
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* If this is true and a older instruction sees it, this instruction must
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* reexecute
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*/
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bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
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void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
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/**
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* Returns true if the DTB address translation is being delayed due to a hw
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* page table walk.
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*/
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bool
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isTranslationDelayed() const
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{
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return (translationStarted() && !translationCompleted());
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}
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public:
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#ifdef DEBUG
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void dumpSNList();
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#endif
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/** Renames a destination register to a physical register. Also records
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* the previous physical register that the logical register mapped to.
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*/
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void
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renameDestReg(int idx, PhysRegIdPtr renamed_dest,
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PhysRegIdPtr previous_rename)
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{
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regs.renamedDestIdx(idx, renamed_dest);
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regs.prevDestIdx(idx, previous_rename);
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if (renamed_dest->isPinned())
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setPinnedRegsRenamed();
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}
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/** Renames a source logical register to the physical register which
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* has/will produce that logical register's result.
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* @todo: add in whether or not the source register is ready.
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*/
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void
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renameSrcReg(int idx, PhysRegIdPtr renamed_src)
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{
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regs.renamedSrcIdx(idx, renamed_src);
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}
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/** BaseDynInst constructor given a binary instruction.
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* @param staticInst A StaticInstPtr to the underlying instruction.
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* @param pc The PC state for the instruction.
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* @param predPC The predicted next PC state for the instruction.
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* @param seq_num The sequence number of the instruction.
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* @param cpu Pointer to the instruction's CPU.
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*/
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BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop,
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TheISA::PCState pc, TheISA::PCState predPC,
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InstSeqNum seq_num, ImplCPU *cpu);
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/** BaseDynInst constructor given a StaticInst pointer.
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* @param _staticInst The StaticInst for this BaseDynInst.
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*/
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BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop);
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/** BaseDynInst destructor. */
|
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~BaseDynInst();
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private:
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/** Function to initialize variables in the constructors. */
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void initVars();
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public:
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/** Dumps out contents of this BaseDynInst. */
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void dump();
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/** Dumps out contents of this BaseDynInst into given string. */
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void dump(std::string &outstring);
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/** Read this CPU's ID. */
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int cpuId() const { return cpu->cpuId(); }
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/** Read this CPU's Socket ID. */
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|
uint32_t socketId() const { return cpu->socketId(); }
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|
|
/** Read this CPU's data requestor ID */
|
|
RequestorID requestorId() const { return cpu->dataRequestorId(); }
|
|
|
|
/** Read this context's system-wide ID **/
|
|
ContextID contextId() const { return thread->contextId(); }
|
|
|
|
/** Returns the fault type. */
|
|
Fault getFault() const { return fault; }
|
|
/** TODO: This I added for the LSQRequest side to be able to modify the
|
|
* fault. There should be a better mechanism in place. */
|
|
Fault& getFault() { return fault; }
|
|
|
|
/** Checks whether or not this instruction has had its branch target
|
|
* calculated yet. For now it is not utilized and is hacked to be
|
|
* always false.
|
|
* @todo: Actually use this instruction.
|
|
*/
|
|
bool doneTargCalc() { return false; }
|
|
|
|
/** Set the predicted target of this current instruction. */
|
|
void setPredTarg(const TheISA::PCState &_predPC) { predPC = _predPC; }
|
|
|
|
const TheISA::PCState &readPredTarg() { return predPC; }
|
|
|
|
/** Returns the predicted PC immediately after the branch. */
|
|
Addr predInstAddr() { return predPC.instAddr(); }
|
|
|
|
/** Returns the predicted PC two instructions after the branch */
|
|
Addr predNextInstAddr() { return predPC.nextInstAddr(); }
|
|
|
|
/** Returns the predicted micro PC after the branch */
|
|
Addr predMicroPC() { return predPC.microPC(); }
|
|
|
|
/** Returns whether the instruction was predicted taken or not. */
|
|
bool readPredTaken() { return instFlags[PredTaken]; }
|
|
|
|
void
|
|
setPredTaken(bool predicted_taken)
|
|
{
|
|
instFlags[PredTaken] = predicted_taken;
|
|
}
|
|
|
|
/** Returns whether the instruction mispredicted. */
|
|
bool
|
|
mispredicted()
|
|
{
|
|
TheISA::PCState tempPC = pc;
|
|
TheISA::advancePC(tempPC, staticInst);
|
|
return !(tempPC == predPC);
|
|
}
|
|
|
|
//
|
|
// Instruction types. Forward checks to StaticInst object.
|
|
//
|
|
bool isNop() const { return staticInst->isNop(); }
|
|
bool isMemRef() const { return staticInst->isMemRef(); }
|
|
bool isLoad() const { return staticInst->isLoad(); }
|
|
bool isStore() const { return staticInst->isStore(); }
|
|
bool isAtomic() const { return staticInst->isAtomic(); }
|
|
bool isStoreConditional() const
|
|
{ return staticInst->isStoreConditional(); }
|
|
bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
|
|
bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
|
|
bool isInteger() const { return staticInst->isInteger(); }
|
|
bool isFloating() const { return staticInst->isFloating(); }
|
|
bool isVector() const { return staticInst->isVector(); }
|
|
bool isControl() const { return staticInst->isControl(); }
|
|
bool isCall() const { return staticInst->isCall(); }
|
|
bool isReturn() const { return staticInst->isReturn(); }
|
|
bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
|
|
bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
|
|
bool isCondCtrl() const { return staticInst->isCondCtrl(); }
|
|
bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
|
|
bool isSerializing() const { return staticInst->isSerializing(); }
|
|
bool
|
|
isSerializeBefore() const
|
|
{
|
|
return staticInst->isSerializeBefore() || status[SerializeBefore];
|
|
}
|
|
bool
|
|
isSerializeAfter() const
|
|
{
|
|
return staticInst->isSerializeAfter() || status[SerializeAfter];
|
|
}
|
|
bool isSquashAfter() const { return staticInst->isSquashAfter(); }
|
|
bool isFullMemBarrier() const { return staticInst->isFullMemBarrier(); }
|
|
bool isReadBarrier() const { return staticInst->isReadBarrier(); }
|
|
bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
|
|
bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
|
|
bool isQuiesce() const { return staticInst->isQuiesce(); }
|
|
bool isUnverifiable() const { return staticInst->isUnverifiable(); }
|
|
bool isSyscall() const { return staticInst->isSyscall(); }
|
|
bool isMacroop() const { return staticInst->isMacroop(); }
|
|
bool isMicroop() const { return staticInst->isMicroop(); }
|
|
bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
|
|
bool isLastMicroop() const { return staticInst->isLastMicroop(); }
|
|
bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
|
|
// hardware transactional memory
|
|
bool isHtmStart() const { return staticInst->isHtmStart(); }
|
|
bool isHtmStop() const { return staticInst->isHtmStop(); }
|
|
bool isHtmCancel() const { return staticInst->isHtmCancel(); }
|
|
bool isHtmCmd() const { return staticInst->isHtmCmd(); }
|
|
|
|
uint64_t
|
|
getHtmTransactionUid() const override
|
|
{
|
|
assert(instFlags[HtmFromTransaction]);
|
|
return this->htmUid;
|
|
}
|
|
|
|
uint64_t
|
|
newHtmTransactionUid() const override
|
|
{
|
|
panic("Not yet implemented\n");
|
|
return 0;
|
|
}
|
|
|
|
bool
|
|
inHtmTransactionalState() const override
|
|
{
|
|
return instFlags[HtmFromTransaction];
|
|
}
|
|
|
|
uint64_t
|
|
getHtmTransactionalDepth() const override
|
|
{
|
|
if (inHtmTransactionalState())
|
|
return this->htmDepth;
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth)
|
|
{
|
|
instFlags.set(HtmFromTransaction);
|
|
htmUid = htm_uid;
|
|
htmDepth = htm_depth;
|
|
}
|
|
|
|
void
|
|
clearHtmTransactionalState()
|
|
{
|
|
if (inHtmTransactionalState()) {
|
|
DPRINTF(HtmCpu,
|
|
"clearing instuction's transactional state htmUid=%u\n",
|
|
getHtmTransactionUid());
|
|
|
|
instFlags.reset(HtmFromTransaction);
|
|
htmUid = -1;
|
|
htmDepth = 0;
|
|
}
|
|
}
|
|
|
|
/** Temporarily sets this instruction as a serialize before instruction. */
|
|
void setSerializeBefore() { status.set(SerializeBefore); }
|
|
|
|
/** Clears the serializeBefore part of this instruction. */
|
|
void clearSerializeBefore() { status.reset(SerializeBefore); }
|
|
|
|
/** Checks if this serializeBefore is only temporarily set. */
|
|
bool isTempSerializeBefore() { return status[SerializeBefore]; }
|
|
|
|
/** Temporarily sets this instruction as a serialize after instruction. */
|
|
void setSerializeAfter() { status.set(SerializeAfter); }
|
|
|
|
/** Clears the serializeAfter part of this instruction.*/
|
|
void clearSerializeAfter() { status.reset(SerializeAfter); }
|
|
|
|
/** Checks if this serializeAfter is only temporarily set. */
|
|
bool isTempSerializeAfter() { return status[SerializeAfter]; }
|
|
|
|
/** Sets the serialization part of this instruction as handled. */
|
|
void setSerializeHandled() { status.set(SerializeHandled); }
|
|
|
|
/** Checks if the serialization part of this instruction has been
|
|
* handled. This does not apply to the temporary serializing
|
|
* state; it only applies to this instruction's own permanent
|
|
* serializing state.
|
|
*/
|
|
bool isSerializeHandled() { return status[SerializeHandled]; }
|
|
|
|
/** Returns the opclass of this instruction. */
|
|
OpClass opClass() const { return staticInst->opClass(); }
|
|
|
|
/** Returns the branch target address. */
|
|
TheISA::PCState
|
|
branchTarget() const
|
|
{
|
|
return staticInst->branchTarget(pc);
|
|
}
|
|
|
|
/** Returns the number of source registers. */
|
|
size_t numSrcRegs() const { return regs.numSrcs(); }
|
|
|
|
/** Returns the number of destination registers. */
|
|
size_t numDestRegs() const { return regs.numDests(); }
|
|
|
|
// the following are used to track physical register usage
|
|
// for machines with separate int & FP reg files
|
|
int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
|
|
int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
|
|
int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
|
|
int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
|
|
int8_t
|
|
numVecElemDestRegs() const
|
|
{
|
|
return staticInst->numVecElemDestRegs();
|
|
}
|
|
int8_t
|
|
numVecPredDestRegs() const
|
|
{
|
|
return staticInst->numVecPredDestRegs();
|
|
}
|
|
|
|
/** Returns the logical register index of the i'th destination register. */
|
|
const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
|
|
|
|
/** Returns the logical register index of the i'th source register. */
|
|
const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
|
|
|
|
/** Return the size of the instResult queue. */
|
|
uint8_t resultSize() { return instResult.size(); }
|
|
|
|
/** Pops a result off the instResult queue.
|
|
* If the result stack is empty, return the default value.
|
|
* */
|
|
InstResult
|
|
popResult(InstResult dflt=InstResult())
|
|
{
|
|
if (!instResult.empty()) {
|
|
InstResult t = instResult.front();
|
|
instResult.pop();
|
|
return t;
|
|
}
|
|
return dflt;
|
|
}
|
|
|
|
/** Pushes a result onto the instResult queue. */
|
|
/** @{ */
|
|
/** Scalar result. */
|
|
template<typename T>
|
|
void
|
|
setScalarResult(T &&t)
|
|
{
|
|
if (instFlags[RecordResult]) {
|
|
instResult.push(InstResult(std::forward<T>(t),
|
|
InstResult::ResultType::Scalar));
|
|
}
|
|
}
|
|
|
|
/** Full vector result. */
|
|
template<typename T>
|
|
void
|
|
setVecResult(T &&t)
|
|
{
|
|
if (instFlags[RecordResult]) {
|
|
instResult.push(InstResult(std::forward<T>(t),
|
|
InstResult::ResultType::VecReg));
|
|
}
|
|
}
|
|
|
|
/** Vector element result. */
|
|
template<typename T>
|
|
void
|
|
setVecElemResult(T &&t)
|
|
{
|
|
if (instFlags[RecordResult]) {
|
|
instResult.push(InstResult(std::forward<T>(t),
|
|
InstResult::ResultType::VecElem));
|
|
}
|
|
}
|
|
|
|
/** Predicate result. */
|
|
template<typename T>
|
|
void
|
|
setVecPredResult(T &&t)
|
|
{
|
|
if (instFlags[RecordResult]) {
|
|
instResult.push(InstResult(std::forward<T>(t),
|
|
InstResult::ResultType::VecPredReg));
|
|
}
|
|
}
|
|
/** @} */
|
|
|
|
/** Records an integer register being set to a value. */
|
|
void
|
|
setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
|
|
{
|
|
setScalarResult(val);
|
|
}
|
|
|
|
/** Records a CC register being set to a value. */
|
|
void
|
|
setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
|
|
{
|
|
setScalarResult(val);
|
|
}
|
|
|
|
/** Record a vector register being set to a value */
|
|
void
|
|
setVecRegOperand(const StaticInst *si, int idx,
|
|
const TheISA::VecRegContainer &val) override
|
|
{
|
|
setVecResult(val);
|
|
}
|
|
|
|
/** Records an fp register being set to an integer value. */
|
|
void
|
|
setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
|
|
{
|
|
setScalarResult(val);
|
|
}
|
|
|
|
/** Record a vector register being set to a value */
|
|
void
|
|
setVecElemOperand(const StaticInst *si, int idx,
|
|
const TheISA::VecElem val) override
|
|
{
|
|
setVecElemResult(val);
|
|
}
|
|
|
|
/** Record a vector register being set to a value */
|
|
void
|
|
setVecPredRegOperand(const StaticInst *si, int idx,
|
|
const TheISA::VecPredRegContainer &val) override
|
|
{
|
|
setVecPredResult(val);
|
|
}
|
|
|
|
/** Records that one of the source registers is ready. */
|
|
void markSrcRegReady();
|
|
|
|
/** Marks a specific register as ready. */
|
|
void markSrcRegReady(RegIndex src_idx);
|
|
|
|
/** Sets this instruction as completed. */
|
|
void setCompleted() { status.set(Completed); }
|
|
|
|
/** Returns whether or not this instruction is completed. */
|
|
bool isCompleted() const { return status[Completed]; }
|
|
|
|
/** Marks the result as ready. */
|
|
void setResultReady() { status.set(ResultReady); }
|
|
|
|
/** Returns whether or not the result is ready. */
|
|
bool isResultReady() const { return status[ResultReady]; }
|
|
|
|
/** Sets this instruction as ready to issue. */
|
|
void setCanIssue() { status.set(CanIssue); }
|
|
|
|
/** Returns whether or not this instruction is ready to issue. */
|
|
bool readyToIssue() const { return status[CanIssue]; }
|
|
|
|
/** Clears this instruction being able to issue. */
|
|
void clearCanIssue() { status.reset(CanIssue); }
|
|
|
|
/** Sets this instruction as issued from the IQ. */
|
|
void setIssued() { status.set(Issued); }
|
|
|
|
/** Returns whether or not this instruction has issued. */
|
|
bool isIssued() const { return status[Issued]; }
|
|
|
|
/** Clears this instruction as being issued. */
|
|
void clearIssued() { status.reset(Issued); }
|
|
|
|
/** Sets this instruction as executed. */
|
|
void setExecuted() { status.set(Executed); }
|
|
|
|
/** Returns whether or not this instruction has executed. */
|
|
bool isExecuted() const { return status[Executed]; }
|
|
|
|
/** Sets this instruction as ready to commit. */
|
|
void setCanCommit() { status.set(CanCommit); }
|
|
|
|
/** Clears this instruction as being ready to commit. */
|
|
void clearCanCommit() { status.reset(CanCommit); }
|
|
|
|
/** Returns whether or not this instruction is ready to commit. */
|
|
bool readyToCommit() const { return status[CanCommit]; }
|
|
|
|
void setAtCommit() { status.set(AtCommit); }
|
|
|
|
bool isAtCommit() { return status[AtCommit]; }
|
|
|
|
/** Sets this instruction as committed. */
|
|
void setCommitted() { status.set(Committed); }
|
|
|
|
/** Returns whether or not this instruction is committed. */
|
|
bool isCommitted() const { return status[Committed]; }
|
|
|
|
/** Sets this instruction as squashed. */
|
|
void setSquashed();
|
|
|
|
/** Returns whether or not this instruction is squashed. */
|
|
bool isSquashed() const { return status[Squashed]; }
|
|
|
|
//Instruction Queue Entry
|
|
//-----------------------
|
|
/** Sets this instruction as a entry the IQ. */
|
|
void setInIQ() { status.set(IqEntry); }
|
|
|
|
/** Sets this instruction as a entry the IQ. */
|
|
void clearInIQ() { status.reset(IqEntry); }
|
|
|
|
/** Returns whether or not this instruction has issued. */
|
|
bool isInIQ() const { return status[IqEntry]; }
|
|
|
|
/** Sets this instruction as squashed in the IQ. */
|
|
void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
|
|
|
|
/** Returns whether or not this instruction is squashed in the IQ. */
|
|
bool isSquashedInIQ() const { return status[SquashedInIQ]; }
|
|
|
|
|
|
//Load / Store Queue Functions
|
|
//-----------------------
|
|
/** Sets this instruction as a entry the LSQ. */
|
|
void setInLSQ() { status.set(LsqEntry); }
|
|
|
|
/** Sets this instruction as a entry the LSQ. */
|
|
void removeInLSQ() { status.reset(LsqEntry); }
|
|
|
|
/** Returns whether or not this instruction is in the LSQ. */
|
|
bool isInLSQ() const { return status[LsqEntry]; }
|
|
|
|
/** Sets this instruction as squashed in the LSQ. */
|
|
void setSquashedInLSQ() { status.set(SquashedInLSQ); status.set(Squashed);}
|
|
|
|
/** Returns whether or not this instruction is squashed in the LSQ. */
|
|
bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
|
|
|
|
|
|
//Reorder Buffer Functions
|
|
//-----------------------
|
|
/** Sets this instruction as a entry the ROB. */
|
|
void setInROB() { status.set(RobEntry); }
|
|
|
|
/** Sets this instruction as a entry the ROB. */
|
|
void clearInROB() { status.reset(RobEntry); }
|
|
|
|
/** Returns whether or not this instruction is in the ROB. */
|
|
bool isInROB() const { return status[RobEntry]; }
|
|
|
|
/** Sets this instruction as squashed in the ROB. */
|
|
void setSquashedInROB() { status.set(SquashedInROB); }
|
|
|
|
/** Returns whether or not this instruction is squashed in the ROB. */
|
|
bool isSquashedInROB() const { return status[SquashedInROB]; }
|
|
|
|
/** Returns whether pinned registers are renamed */
|
|
bool isPinnedRegsRenamed() const { return status[PinnedRegsRenamed]; }
|
|
|
|
/** Sets the destination registers as renamed */
|
|
void
|
|
setPinnedRegsRenamed()
|
|
{
|
|
assert(!status[PinnedRegsSquashDone]);
|
|
assert(!status[PinnedRegsWritten]);
|
|
status.set(PinnedRegsRenamed);
|
|
}
|
|
|
|
/** Returns whether destination registers are written */
|
|
bool isPinnedRegsWritten() const { return status[PinnedRegsWritten]; }
|
|
|
|
/** Sets destination registers as written */
|
|
void
|
|
setPinnedRegsWritten()
|
|
{
|
|
assert(!status[PinnedRegsSquashDone]);
|
|
assert(status[PinnedRegsRenamed]);
|
|
status.set(PinnedRegsWritten);
|
|
}
|
|
|
|
/** Return whether dest registers' pinning status updated after squash */
|
|
bool
|
|
isPinnedRegsSquashDone() const
|
|
{
|
|
return status[PinnedRegsSquashDone];
|
|
}
|
|
|
|
/** Sets dest registers' status updated after squash */
|
|
void
|
|
setPinnedRegsSquashDone()
|
|
{
|
|
assert(!status[PinnedRegsSquashDone]);
|
|
status.set(PinnedRegsSquashDone);
|
|
}
|
|
|
|
/** Read the PC state of this instruction. */
|
|
TheISA::PCState pcState() const override { return pc; }
|
|
|
|
/** Set the PC state of this instruction. */
|
|
void pcState(const TheISA::PCState &val) override { pc = val; }
|
|
|
|
/** Read the PC of this instruction. */
|
|
Addr instAddr() const { return pc.instAddr(); }
|
|
|
|
/** Read the PC of the next instruction. */
|
|
Addr nextInstAddr() const { return pc.nextInstAddr(); }
|
|
|
|
/**Read the micro PC of this instruction. */
|
|
Addr microPC() const { return pc.microPC(); }
|
|
|
|
bool readPredicate() const override { return instFlags[Predicate]; }
|
|
|
|
void
|
|
setPredicate(bool val) override
|
|
{
|
|
instFlags[Predicate] = val;
|
|
|
|
if (traceData) {
|
|
traceData->setPredicate(val);
|
|
}
|
|
}
|
|
|
|
bool
|
|
readMemAccPredicate() const override
|
|
{
|
|
return instFlags[MemAccPredicate];
|
|
}
|
|
|
|
void
|
|
setMemAccPredicate(bool val) override
|
|
{
|
|
instFlags[MemAccPredicate] = val;
|
|
}
|
|
|
|
/** Sets the thread id. */
|
|
void setTid(ThreadID tid) { threadNumber = tid; }
|
|
|
|
/** Sets the pointer to the thread state. */
|
|
void setThreadState(ImplState *state) { thread = state; }
|
|
|
|
/** Returns the thread context. */
|
|
ThreadContext *tcBase() const override { return thread->getTC(); }
|
|
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public:
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/** Returns whether or not the eff. addr. source registers are ready. */
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bool eaSrcsReady() const;
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/** Is this instruction's memory access strictly ordered? */
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bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
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void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; }
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/** Has this instruction generated a memory request. */
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bool hasRequest() const { return instFlags[ReqMade]; }
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/** Assert this instruction has generated a memory request. */
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void setRequest() { instFlags[ReqMade] = true; }
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/** Returns iterator to this instruction in the list of all insts. */
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ListIt &getInstListIt() { return instListIt; }
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/** Sets iterator for this instruction in the list of all insts. */
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void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
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public:
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/** Returns the number of consecutive store conditional failures. */
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unsigned int
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readStCondFailures() const override
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{
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return thread->storeCondFailures;
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}
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/** Sets the number of consecutive store conditional failures. */
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void
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setStCondFailures(unsigned int sc_failures) override
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{
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thread->storeCondFailures = sc_failures;
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}
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public:
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// monitor/mwait funtions
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void
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armMonitor(Addr address) override
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{
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cpu->armMonitor(threadNumber, address);
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}
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bool
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mwait(PacketPtr pkt) override
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{
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return cpu->mwait(threadNumber, pkt);
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}
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void
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mwaitAtomic(ThreadContext *tc) override
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{
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return cpu->mwaitAtomic(threadNumber, tc, cpu->mmu);
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}
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AddressMonitor *
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getAddrMonitor() override
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{
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return cpu->getCpuAddrMonitor(threadNumber);
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}
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};
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template<class Impl>
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Fault
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BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
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Request::Flags flags,
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const std::vector<bool> &byte_enable)
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{
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assert(byte_enable.size() == size);
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return cpu->pushRequest(
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dynamic_cast<typename DynInstPtr::PtrType>(this),
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/* ld */ true, nullptr, size, addr, flags, nullptr, nullptr,
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byte_enable);
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}
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template<class Impl>
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Fault
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BaseDynInst<Impl>::initiateHtmCmd(Request::Flags flags)
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|
{
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return cpu->pushRequest(
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dynamic_cast<typename DynInstPtr::PtrType>(this),
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/* ld */ true, nullptr, 8, 0x0ul, flags, nullptr, nullptr);
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}
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|
template<class Impl>
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Fault
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BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
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|
Request::Flags flags, uint64_t *res,
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const std::vector<bool> &byte_enable)
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|
{
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|
assert(byte_enable.size() == size);
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|
return cpu->pushRequest(
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|
dynamic_cast<typename DynInstPtr::PtrType>(this),
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|
/* st */ false, data, size, addr, flags, res, nullptr,
|
|
byte_enable);
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}
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|
|
template<class Impl>
|
|
Fault
|
|
BaseDynInst<Impl>::initiateMemAMO(Addr addr, unsigned size,
|
|
Request::Flags flags,
|
|
AtomicOpFunctorPtr amo_op)
|
|
{
|
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// atomic memory instructions do not have data to be written to memory yet
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// since the atomic operations will be executed directly in cache/memory.
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// Therefore, its `data` field is nullptr.
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|
// Atomic memory requests need to carry their `amo_op` fields to cache/
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// memory
|
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return cpu->pushRequest(
|
|
dynamic_cast<typename DynInstPtr::PtrType>(this),
|
|
/* atomic */ false, nullptr, size, addr, flags, nullptr,
|
|
std::move(amo_op), std::vector<bool>(size, true));
|
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}
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#endif // __CPU_BASE_DYN_INST_HH__
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