479ca6a895
Change-Id: I6e9f5b70faebe5d279bff303c42f59a00a7845ec Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25447 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
105 lines
4.3 KiB
Python
105 lines
4.3 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2009, 2013, 2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.SimObject import SimObject
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from m5.params import *
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from m5.proxy import *
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from m5.objects.BaseTLB import BaseTLB
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from m5.objects.ClockedObject import ClockedObject
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# Basic stage 1 translation objects
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class ArmTableWalker(ClockedObject):
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type = 'ArmTableWalker'
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cxx_class = 'ArmISA::TableWalker'
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cxx_header = "arch/arm/table_walker.hh"
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is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?")
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num_squash_per_cycle = Param.Unsigned(2,
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"Number of outstanding walks that can be squashed per cycle")
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# The port to the memory system. This port is ultimately belonging
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# to the Stage2MMU, and shared by the two table walkers, but we
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# access it through the ITB and DTB walked objects in the CPU for
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# symmetry with the other ISAs.
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port = MasterPort("Port used by the two table walkers")
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sys = Param.System(Parent.any, "system object parameter")
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class ArmTLB(BaseTLB):
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type = 'ArmTLB'
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cxx_class = 'ArmISA::TLB'
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cxx_header = "arch/arm/tlb.hh"
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sys = Param.System(Parent.any, "system object parameter")
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size = Param.Int(64, "TLB size")
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walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
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is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?")
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# Stage 2 translation objects, only used when virtualisation is being used
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class ArmStage2TableWalker(ArmTableWalker):
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is_stage2 = True
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class ArmStage2TLB(ArmTLB):
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size = 32
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walker = ArmStage2TableWalker()
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is_stage2 = True
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class ArmStage2MMU(SimObject):
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type = 'ArmStage2MMU'
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cxx_class = 'ArmISA::Stage2MMU'
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cxx_header = 'arch/arm/stage2_mmu.hh'
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tlb = Param.ArmTLB("Stage 1 TLB")
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stage2_tlb = Param.ArmTLB("Stage 2 TLB")
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sys = Param.System(Parent.any, "system object parameter")
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class ArmStage2IMMU(ArmStage2MMU):
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# We rely on the itb being a parameter of the CPU, and get the
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# appropriate object that way
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tlb = Parent.any
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stage2_tlb = ArmStage2TLB()
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class ArmStage2DMMU(ArmStage2MMU):
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# We rely on the dtb being a parameter of the CPU, and get the
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# appropriate object that way
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tlb = Parent.any
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stage2_tlb = ArmStage2TLB()
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class ArmITB(ArmTLB):
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stage2_mmu = ArmStage2IMMU()
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class ArmDTB(ArmTLB):
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stage2_mmu = ArmStage2DMMU()
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