Gabe Black 119f5f8e94 X86: Add L1 caches for the TLB walkers. ...

Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.

2011-02-01 18:28:41 -08:00

..

Benchmarks.py

style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs

2008-09-10 14:26:15 -04:00

CacheConfig.py

X86: Add L1 caches for the TLB walkers.

2011-02-01 18:28:41 -08:00

Caches.py

X86: Add L1 caches for the TLB walkers.

2011-02-01 18:28:41 -08:00

cpu2000.py

ARM: fix sizes of structs for ARM Linux

2010-06-02 12:58:17 -05:00

FSConfig.py

ARM: Add support for a dumb IDE controller

2010-11-15 14:04:03 -06:00

Options.py

ruby: Reduced ruby latencies

2010-08-20 11:46:12 -07:00

Simulation.py

Config: Change misleading "cycle" message to say "tick".

2010-11-17 23:16:19 -05:00

SysPaths.py

make rcS files read from the m5 source directory, not /dist.

2006-11-08 14:10:25 -05:00