13a15c55a4
Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
32 lines
1.0 KiB
Plaintext
Executable File
32 lines
1.0 KiB
Plaintext
Executable File
M5 Simulator System
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Copyright (c) 2001-2008
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The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Sep 20 2010 15:04:50
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M5 revision 0c4a7d867247 7686 default qtip print-identical tip
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M5 started Sep 20 2010 15:14:22
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M5 executing on phenom
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command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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MCF SPEC version 1.6.I
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by Andreas Loebel
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Copyright (c) 1998,1999 ZIB Berlin
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All Rights Reserved.
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nodes : 500
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active arcs : 1905
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simplex iterations : 1502
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flow value : 4990014995
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new implicit arcs : 23867
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active arcs : 25772
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simplex iterations : 2663
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flow value : 3080014995
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checksum : 68389
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optimal
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Exiting @ tick 148086219000 because target called exit()
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