Nilay Vaish 0ef3dcc27b x86: decode instructions with vex prefix ...

This patch updates the x86 decoder so that it can decode instructions with vex
prefix. It also updates the isa with opcodes from vex opcode maps 1, 2 and 3.
Note that none of the instructions have been implemented yet. The
implementations would be provided in due course of time.

2015-07-17 11:31:22 -05:00

..

arch

x86: decode instructions with vex prefix

2015-07-17 11:31:22 -05:00

base

base: Add serialization support to Pixels and FrameBuffer

2015-07-07 09:51:04 +01:00

cpu

ruby: replace global g_abs_controls with per-RubySystem var

2015-07-10 16:05:24 -05:00

dev

dev: add support for multi gem5 runs

2015-07-15 19:53:50 -05:00

doc

cpu: `Minor' in-order CPU model

2014-07-23 16:09:04 -05:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

kern

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

mem

mem: Fix (ab)use of emplace to avoid temporary object creation

2015-07-13 08:46:28 -04:00

proto

cpu: add support for outputing a protobuf formatted CPU trace

2015-02-16 03:32:38 -05:00

python

sim: Decouple draining from the SimObject hierarchy

2015-07-07 09:51:05 +01:00

sim

sim: Refactor and simplify the drain API

2015-07-07 09:51:05 +01:00

unittest

base: Redesign internal frame buffer handling

2015-05-23 13:37:03 +01:00

Doxyfile

Doxygen: Update the version of the Doxyfile

2012-10-11 06:38:42 -04:00

SConscript

scons: Bump compiler requirement to gcc >= 4.7 and clang >= 3.1

2015-07-03 10:14:15 -04:00