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0dd1f7f01a8a744811aede5814111b8681271a6b
gem5/src/cpu
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Gabe Black 0dd1f7f01a CPU: Trim unnecessary includes from some common files. 
This reduces the scope of those includes and makes it less likely for there to
be a dependency loop. This also moves the hashing functions associated with
ExtMachInst objects to be with the ExtMachInst definitions and out of
utility.hh.
2010-09-14 00:29:38 -07:00
..
checker
CPU: Get rid of the now unnecessary getInst/setInst family of functions.
2010-09-13 21:58:34 -07:00
inorder
CPU: Get rid of the now unnecessary getInst/setInst family of functions.
2010-09-13 21:58:34 -07:00
o3
CPU: Get rid of the now unnecessary getInst/setInst family of functions.
2010-09-13 21:58:34 -07:00
ozone
CPU: Get rid of the now unnecessary getInst/setInst family of functions.
2010-09-13 21:58:34 -07:00
pred
BPRED: Fixed the treshold-bug in the tournament predictor.
2010-05-13 23:45:57 -04:00
simple
CPU: Get rid of the now unnecessary getInst/setInst family of functions.
2010-09-13 21:58:34 -07:00
testers
memtest: fix/cleanup functional access testing
2010-08-25 21:55:44 -07:00
trace
request: rename INST_READ to INST_FETCH.
2009-04-20 18:54:02 -07:00
activity.cc
o3cpu: give a name to the activity recorder for better tracing
2009-01-21 14:56:18 -08:00
activity.hh
o3cpu: give a name to the activity recorder for better tracing
2009-01-21 14:56:18 -08:00
base_dyn_inst_impl.hh
ARM: mark msr/mrs instructions as SerializeBefore/After
2010-08-23 11:18:41 -05:00
base_dyn_inst.hh
Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.
2010-09-13 19:26:03 -07:00
base.cc
commit Soumyaroop's bug catch about max_insts_all_threads
2009-09-29 18:03:10 -04:00
base.hh
tick: rename Clock namespace to SimClock
2010-04-15 16:24:12 -07:00
BaseCPU.py
ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.
2010-06-02 12:58:16 -05:00
CheckerCPU.py
python: Move more code into m5.util allow SCons to use that code.
2009-09-22 15:24:16 -07:00
cpuevent.cc
…
cpuevent.hh
eventq: convert all usage of events to use the new API.
2008-10-09 04:58:24 -07:00
exec_context.hh
CPU: Add readBytes and writeBytes functions to the exec contexts.
2010-08-13 06:16:02 -07:00
exetrace.cc
CPU: Trim unnecessary includes from some common files.
2010-09-14 00:29:38 -07:00
exetrace.hh
CPU: Trim unnecessary includes from some common files.
2010-09-14 00:29:38 -07:00
ExeTracer.py
SimObjects: Clean up handling of C++ namespaces.
2008-10-09 22:19:39 -07:00
func_unit.cc
params: Deprecate old-style constructors; update most SimObject constructors.
2007-08-30 15:16:59 -04:00
func_unit.hh
params: Deprecate old-style constructors; update most SimObject constructors.
2007-08-30 15:16:59 -04:00
FuncUnit.py
Rename enum from OpType to OpClass so it's consistent with the
2007-06-11 23:10:58 -07:00
inst_seq.hh
build: fix compile problems pointed out by gcc 4.4
2009-11-04 16:57:01 -08:00
inteltrace.cc
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
2009-09-23 08:34:21 -07:00
inteltrace.hh
includes: sort includes again
2009-05-17 14:34:52 -07:00
IntelTrace.py
SimObjects: Clean up handling of C++ namespaces.
2008-10-09 22:19:39 -07:00
intr_control.cc
style: Use the correct m5 style for things relating to interrupts.
2008-10-21 07:12:53 -07:00
intr_control.hh
Interrupts: Inline some code and remove duplication.
2007-11-08 10:46:41 -05:00
IntrControl.py
Move SimObject python files alongside the C++ and fix
2007-05-27 19:21:17 -07:00
legiontrace.cc
build: fix compile problems pointed out by gcc 4.4
2009-11-04 16:57:01 -08:00
legiontrace.hh
includes: sort includes again
2009-05-17 14:34:52 -07:00
LegionTrace.py
SimObjects: Clean up handling of C++ namespaces.
2008-10-09 22:19:39 -07:00
m5legion_interface.h
add fsr to the list of registers we are interested in
2007-01-30 18:27:04 -05:00
nativetrace.cc
ARM: Make native trace print out what instruction caused an error.
2009-07-27 00:54:09 -07:00
nativetrace.hh
ARM: Make native trace print out what instruction caused an error.
2009-07-27 00:54:09 -07:00
NativeTrace.py
ARM: Make native trace print out what instruction caused an error.
2009-07-27 00:54:09 -07:00
op_class.hh
Major changes to how SimObjects are created and initialized. Almost all
2007-07-23 21:51:38 -07:00
pc_event.cc
debug: Move debug_break into src/base
2009-02-23 11:48:40 -08:00
pc_event.hh
types: Move stuff for global types into src/base/types.hh
2009-05-17 14:34:50 -07:00
profile.cc
…
profile.hh
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
2009-09-23 08:34:21 -07:00
quiesce_event.cc
eventq: convert all usage of events to use the new API.
2008-10-09 04:58:24 -07:00
quiesce_event.hh
Make the Event::description() a const function
2008-02-06 16:32:40 -05:00
SConscript
cpu_models: get rid of cpu_models.py and move the stuff into SCons
2010-02-26 18:14:48 -08:00
simple_thread.cc
CPU: Trim unnecessary includes from some common files.
2010-09-14 00:29:38 -07:00
simple_thread.hh
Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.
2010-09-13 19:26:03 -07:00
smt.hh
types: add a type for thread IDs and try to use it everywhere
2009-05-26 09:23:13 -07:00
static_inst.cc
inorder-tlb-cunit: merge the TLB as implicit to any memory access
2009-05-12 15:01:16 -04:00
static_inst.hh
CPU: Trim unnecessary includes from some common files.
2010-09-14 00:29:38 -07:00
thread_context.cc
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
2009-09-23 08:34:21 -07:00
thread_context.hh
CPU: Trim unnecessary includes from some common files.
2010-09-14 00:29:38 -07:00
thread_state.cc
CPU: Get rid of the now unnecessary getInst/setInst family of functions.
2010-09-13 21:58:34 -07:00
thread_state.hh
CPU: Get rid of the now unnecessary getInst/setInst family of functions.
2010-09-13 21:58:34 -07:00
translation.hh
Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.
2010-09-13 19:26:03 -07:00