Gabe Black 0cba96ba6a CPU: Merge the predecoder and decoder. ...

These classes are always used together, and merging them will give the ISAs
more flexibility in how they cache things and manage the process.

--HG--
rename : src/arch/x86/predecoder_tables.cc => src/arch/x86/decoder_tables.cc

2012-05-26 13:44:46 -07:00

..

atomic.cc

CPU: Merge the predecoder and decoder.

2012-05-26 13:44:46 -07:00

atomic.hh

MEM: Separate snoops and normal memory requests/responses

2012-04-14 05:45:07 -04:00

AtomicSimpleCPU.py

Atomic: Remove the physmem_port and access memory directly

2012-04-03 03:50:14 -04:00

base.cc

CPU: Merge the predecoder and decoder.

2012-05-26 13:44:46 -07:00

base.hh

CPU: Merge the predecoder and decoder.

2012-05-26 13:44:46 -07:00

BaseSimpleCPU.py

CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable

2012-03-09 09:59:27 -05:00

SConscript

scons: rename TraceFlags to DebugFlags

2011-06-02 17:36:21 -07:00

SConsopts

cpu_models: get rid of cpu_models.py and move the stuff into SCons

2010-02-26 18:14:48 -08:00

timing.cc

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

timing.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

TimingSimpleCPU.py

CPU: Moving towards a more general port across CPU models

2012-01-17 12:55:08 -06:00