4e75e35a33
ArmSigInterruptPin don't send the interrupt to GIC. Instead it sends the interrupt to the irq specified in Param. When using ArmSigInterruptPin, we shouldn't ask users to provide "Platform" since it doesn't need it. To reduce the confusion, this change removes the dependency of Platform for ArmSigInterruptPin. Change-Id: I0ee507ed1c08b4fa6d3e384e28732f3acb4f6892
382 lines
13 KiB
Python
382 lines
13 KiB
Python
# Copyright (c) 2012-2013, 2017-2020 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.objects.Device import (
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BasicPioDevice,
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PioDevice,
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)
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from m5.objects.IntPin import IntSourcePin
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from m5.objects.Platform import Platform
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from m5.params import *
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from m5.proxy import *
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from m5.SimObject import SimObject
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from m5.util.fdthelper import *
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class BaseGic(PioDevice):
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type = "BaseGic"
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abstract = True
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cxx_header = "dev/arm/base_gic.hh"
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cxx_class = "gem5::BaseGic"
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# Used for DTB autogeneration
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_state = FdtState(addr_cells=0, interrupt_cells=3)
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platform = Param.Platform(Parent.any, "Platform this device is part of.")
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gicd_iidr = Param.UInt32(
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0, "Distributor Implementer Identification Register"
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)
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gicd_pidr = Param.UInt32(0, "Peripheral Identification Register")
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gicc_iidr = Param.UInt32(0, "CPU Interface Identification Register")
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gicv_iidr = Param.UInt32(0, "VM CPU Interface Identification Register")
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def interruptCells(self, int_type, int_num, int_trigger, partition=None):
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"""
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Interupt cells generation helper:
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Following specifications described in
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Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
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"""
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assert self._state.interrupt_cells == 3
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# Check for affinity in case of PPI. If there is no PPI
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# partitioning, set the affinity to target all CPUs
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# (affinity = 0xf00)
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if partition is None and int_type == ArmPPI._LINUX_ID:
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affinity = 0xF00
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else:
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affinity = 0
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return [int_type, int_num, affinity | int_trigger]
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class ArmInterruptType(ScopedEnum):
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"""
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The values of the scoped enum are matching Linux macroes
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defined in include/linux/irq.h. They are mainly meant
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to be used for DTB autogen
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"""
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map = {
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"IRQ_TYPE_EDGE_RISING": 0x1,
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"IRQ_TYPE_EDGE_FALLING": 0x2,
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"IRQ_TYPE_LEVEL_HIGH": 0x4,
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"IRQ_TYPE_LEVEL_LOW": 0x8,
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}
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class ArmInterruptPin(SimObject):
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type = "ArmInterruptPin"
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cxx_header = "dev/arm/base_gic.hh"
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cxx_class = "gem5::ArmInterruptPinGen"
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abstract = True
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platform = Param.Platform(Parent.any, "Platform with interrupt controller")
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num = Param.UInt32("Interrupt number in GIC")
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int_type = Param.ArmInterruptType(
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"IRQ_TYPE_LEVEL_HIGH", "Interrupt type (level/edge triggered)"
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)
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class ArmSPI(ArmInterruptPin):
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type = "ArmSPI"
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cxx_header = "dev/arm/base_gic.hh"
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cxx_class = "gem5::ArmSPIGen"
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_LINUX_ID = 0
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def generateFdtProperty(self, gic):
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"""
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Return a list used as an entry for an interrupt FdtProperty
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Subtracting 32 because Linux assumes that SPIs start at 0, while
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gem5 uses the internal GIC numbering (SPIs start at 32)
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"""
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return gic.interruptCells(
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self._LINUX_ID, self.num - 32, int(self.int_type.getValue())
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)
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class ArmPPI(ArmInterruptPin):
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type = "ArmPPI"
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cxx_header = "dev/arm/base_gic.hh"
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cxx_class = "gem5::ArmPPIGen"
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_LINUX_ID = 1
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def generateFdtProperty(self, gic):
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"""
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Return a list used as an entry for an interrupt FdtProperty
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Subtracting 16 because Linux assumes that PPIs start at 0, while
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gem5 uses the internal GIC numbering (PPIs start at 16)
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"""
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return gic.interruptCells(
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self._LINUX_ID, self.num - 16, int(self.int_type.getValue())
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)
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class ArmSigInterruptPin(ArmInterruptPin):
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type = "ArmSigInterruptPin"
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cxx_header = "dev/arm/base_gic.hh"
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cxx_class = "gem5::ArmSigInterruptPinGen"
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irq = IntSourcePin("Interrupt pin")
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platform = NULL
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class GicV2(BaseGic):
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type = "GicV2"
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cxx_header = "dev/arm/gic_v2.hh"
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cxx_class = "gem5::GicV2"
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dist_addr = Param.Addr("Address for distributor")
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cpu_addr = Param.Addr("Address for cpu")
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cpu_size = Param.Addr(0x2000, "Size of cpu register bank")
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dist_pio_delay = Param.Latency("10ns", "Delay for PIO r/w to distributor")
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cpu_pio_delay = Param.Latency("10ns", "Delay for PIO r/w to cpu interface")
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int_latency = Param.Latency("10ns", "Delay for interrupt to get to CPU")
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it_lines = Param.UInt32(
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128, "Number of interrupt lines supported (max = 1020)"
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)
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gem5_extensions = Param.Bool(False, "Enable gem5 extensions")
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class Gic400(GicV2):
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"""
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As defined in:
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"ARM Generic Interrupt Controller Architecture" version 2.0
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"CoreLink GIC-400 Generic Interrupt Controller" revision r0p1
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"""
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gicd_pidr = 0x002BB490
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gicd_iidr = 0x0200143B
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gicc_iidr = 0x0202143B
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# gicv_iidr same as gicc_idr
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gicv_iidr = gicc_iidr
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class Gicv2mFrame(SimObject):
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type = "Gicv2mFrame"
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cxx_header = "dev/arm/gic_v2m.hh"
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cxx_class = "gem5::Gicv2mFrame"
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spi_base = Param.UInt32(0x0, "Frame SPI base number")
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spi_len = Param.UInt32(0x0, "Frame SPI total number")
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addr = Param.Addr("Address for frame PIO")
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class Gicv2m(PioDevice):
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type = "Gicv2m"
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cxx_header = "dev/arm/gic_v2m.hh"
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cxx_class = "gem5::Gicv2m"
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pio_delay = Param.Latency("10ns", "Delay for PIO r/w")
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gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts")
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frames = VectorParam.Gicv2mFrame([], "Power of two number of frames")
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class VGic(PioDevice):
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type = "VGic"
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cxx_header = "dev/arm/vgic.hh"
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cxx_class = "gem5::VGic"
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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platform = Param.Platform(Parent.any, "Platform this device is part of.")
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vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
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hv_addr = Param.Addr(0, "Address for hv control")
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pio_delay = Param.Latency("10ns", "Delay for PIO r/w")
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# The number of list registers is not currently configurable at runtime.
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maint_int = Param.UInt32("HV maintenance interrupt number")
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# gicv_iidr same as gicc_idr
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gicv_iidr = Param.UInt32(
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Self.gic.gicc_iidr, "VM CPU Interface Identification Register"
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)
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def generateDeviceTree(self, state):
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gic = self.gic.unproxy(self)
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node = FdtNode("interrupt-controller")
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node.appendCompatible(
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["gem5,gic", "arm,cortex-a15-gic", "arm,cortex-a9-gic"]
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)
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node.append(gic._state.interruptCellsProperty())
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node.append(gic._state.addrCellsProperty())
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node.append(FdtProperty("interrupt-controller"))
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regs = (
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state.addrCells(gic.dist_addr)
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+ state.sizeCells(0x1000)
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+ state.addrCells(gic.cpu_addr)
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+ state.sizeCells(0x1000)
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+ state.addrCells(self.hv_addr)
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+ state.sizeCells(0x2000)
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+ state.addrCells(self.vcpu_addr)
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+ state.sizeCells(0x2000)
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)
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node.append(FdtPropertyWords("reg", regs))
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node.append(
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FdtPropertyWords(
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"interrupts", [1, int(self.maint_int) - 16, 0xF04]
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)
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)
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node.appendPhandle(gic)
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yield node
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class Gicv3Its(BasicPioDevice):
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type = "Gicv3Its"
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cxx_header = "dev/arm/gic_v3_its.hh"
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cxx_class = "gem5::Gicv3Its"
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dma = RequestPort("DMA port")
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pio_size = Param.Unsigned(0x20000, "Gicv3Its pio size")
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# CIL [36] = 0: ITS supports 16-bit CollectionID
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# Devbits [17:13] = 0b100011: ITS supports 23 DeviceID bits
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# ID_bits [12:8] = 0b11111: ITS supports 31 EventID bits
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gits_typer = Param.UInt64(0x30023F01, "GITS_TYPER RO value")
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def generateDeviceTree(self, state):
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node = self.generateBasicPioDeviceNode(
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state, "gic-its", self.pio_addr, self.pio_size
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)
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node.appendCompatible(["arm,gic-v3-its"])
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node.append(FdtProperty("msi-controller"))
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node.append(FdtPropertyWords("#msi-cells", [1]))
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return node
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class Gicv3(BaseGic):
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type = "Gicv3"
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cxx_header = "dev/arm/gic_v3.hh"
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cxx_class = "gem5::Gicv3"
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# Used for DTB autogeneration
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_state = FdtState(addr_cells=2, size_cells=2, interrupt_cells=3)
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its = Param.Gicv3Its(NULL, "GICv3 Interrupt Translation Service")
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dist_addr = Param.Addr("Address for distributor")
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dist_pio_delay = Param.Latency("10ns", "Delay for PIO r/w to distributor")
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redist_addr = Param.Addr("Address for redistributors")
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redist_pio_delay = Param.Latency(
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"10ns", "Delay for PIO r/w to redistributors"
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)
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it_lines = Param.UInt32(
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1020, "Number of interrupt lines supported (max = 1020)"
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)
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maint_int = Param.ArmInterruptPin(
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"HV maintenance interrupt."
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"ARM strongly recommends that maintenance interrupts "
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"are configured to use INTID 25 (PPI Interrupt)."
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)
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cpu_max = Param.Unsigned(
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256,
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"Maximum number of PE. This is affecting the maximum number of "
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"redistributors",
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)
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gicv4 = Param.Bool(False, "GIC is GICv4 compatible")
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reserved_is_res0 = Param.Bool(
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True,
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"According to the GIC specification (IHI0069) "
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"reserved addresses in the GIC memory map are treated as RES0. "
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"We allow to disable this behaviour and panic instead "
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"(reserved_res0 = False) to catch development bugs "
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"(in gem5 and in the guest SW)",
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)
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def interruptCells(self, int_type, int_num, int_trigger, partition=None):
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"""
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Interupt cells generation helper:
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Following specifications described in
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Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
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"""
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prop = self._state.interruptCells(0)
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assert len(prop) >= 3
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prop[0] = int_type
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prop[1] = int_num
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prop[2] = int_trigger
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return prop
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def generateDeviceTree(self, state):
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node = FdtNode("interrupt-controller")
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node.appendCompatible(["arm,gic-v3"])
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node.append(self._state.interruptCellsProperty())
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node.append(self._state.addrCellsProperty())
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node.append(self._state.sizeCellsProperty())
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node.append(FdtProperty("ranges"))
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node.append(FdtProperty("interrupt-controller"))
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redist_stride = 0x40000 if self.gicv4 else 0x20000
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node.append(
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FdtPropertyWords(
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"redistributor-stride", state.sizeCells(redist_stride)
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)
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)
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regs = (
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state.addrCells(self.dist_addr)
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+ state.sizeCells(0x10000)
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+ state.addrCells(self.redist_addr)
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+ state.sizeCells(0x2000000)
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)
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node.append(FdtPropertyWords("reg", regs))
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node.append(
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FdtPropertyWords(
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"interrupts",
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self.interruptCells(1, int(self.maint_int.num) - 16, 0x4),
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)
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)
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node.appendPhandle(self)
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# Generate the ITS device tree if instantiated
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if self.its != NULL:
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node.append(self.its.generateDeviceTree(self._state))
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yield node
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