0ad5d1edc5
System calls should now be requested from the workload directly and not routed through ExecContext or ThreadContext interfaces. That removes a major special case for SE mode from those interfaces. For now, when the SE workload gets a request for a system call, it dispatches it to the appropriate Process object. In the future, the ISA specific Workload subclasses will be responsible for handling system calls and not the Process classes. For simplicity, the Workload syscall() method is defined in the base class but will panic everywhere except when SEWorkload overrides it. In the future, this mechanism will turn into a way to request generic services from the workload which are not necessarily system calls. For instance, it could be a way to request handling of a page fault without having to have another PseudoInst just for that purpose. Change-Id: I18d36d64c54adf4f4f17a62e7e006ff2fc0b22f1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33282 Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
590 lines
17 KiB
C++
590 lines
17 KiB
C++
/*
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* Copyright (c) 2014-2018, 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_SIMPLE_EXEC_CONTEXT_HH__
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#define __CPU_SIMPLE_EXEC_CONTEXT_HH__
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#include "arch/registers.hh"
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#include "base/types.hh"
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#include "config/the_isa.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/reg_class.hh"
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#include "cpu/simple/base.hh"
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#include "cpu/static_inst_fwd.hh"
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#include "cpu/translation.hh"
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#include "mem/request.hh"
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class BaseSimpleCPU;
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class SimpleExecContext : public ExecContext {
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protected:
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using VecRegContainer = TheISA::VecRegContainer;
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using VecElem = TheISA::VecElem;
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public:
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BaseSimpleCPU *cpu;
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SimpleThread* thread;
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// This is the offset from the current pc that fetch should be performed
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Addr fetchOffset;
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// This flag says to stay at the current pc. This is useful for
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// instructions which go beyond MachInst boundaries.
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bool stayAtPC;
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// Branch prediction
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TheISA::PCState predPC;
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/** PER-THREAD STATS */
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// Number of simulated instructions
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Counter numInst;
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Stats::Scalar numInsts;
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Counter numOp;
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Stats::Scalar numOps;
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// Number of integer alu accesses
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Stats::Scalar numIntAluAccesses;
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// Number of float alu accesses
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Stats::Scalar numFpAluAccesses;
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// Number of vector alu accesses
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Stats::Scalar numVecAluAccesses;
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// Number of function calls/returns
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Stats::Scalar numCallsReturns;
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// Conditional control instructions;
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Stats::Scalar numCondCtrlInsts;
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// Number of int instructions
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Stats::Scalar numIntInsts;
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// Number of float instructions
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Stats::Scalar numFpInsts;
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// Number of vector instructions
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Stats::Scalar numVecInsts;
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// Number of integer register file accesses
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Stats::Scalar numIntRegReads;
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Stats::Scalar numIntRegWrites;
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// Number of float register file accesses
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Stats::Scalar numFpRegReads;
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Stats::Scalar numFpRegWrites;
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// Number of vector register file accesses
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mutable Stats::Scalar numVecRegReads;
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Stats::Scalar numVecRegWrites;
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// Number of predicate register file accesses
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mutable Stats::Scalar numVecPredRegReads;
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Stats::Scalar numVecPredRegWrites;
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// Number of condition code register file accesses
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Stats::Scalar numCCRegReads;
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Stats::Scalar numCCRegWrites;
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// Number of simulated memory references
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Stats::Scalar numMemRefs;
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Stats::Scalar numLoadInsts;
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Stats::Scalar numStoreInsts;
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// Number of idle cycles
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Stats::Formula numIdleCycles;
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// Number of busy cycles
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Stats::Formula numBusyCycles;
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// Number of simulated loads
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Counter numLoad;
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// Number of idle cycles
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Stats::Average notIdleFraction;
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Stats::Formula idleFraction;
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// Number of cycles stalled for I-cache responses
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Stats::Scalar icacheStallCycles;
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Counter lastIcacheStall;
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// Number of cycles stalled for D-cache responses
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Stats::Scalar dcacheStallCycles;
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Counter lastDcacheStall;
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/// @{
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/// Total number of branches fetched
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Stats::Scalar numBranches;
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/// Number of branches predicted as taken
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Stats::Scalar numPredictedBranches;
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/// Number of misprediced branches
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Stats::Scalar numBranchMispred;
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/// @}
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// Instruction mix histogram by OpClass
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Stats::Vector statExecutedInstType;
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public:
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/** Constructor */
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SimpleExecContext(BaseSimpleCPU* _cpu, SimpleThread* _thread)
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: cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false),
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numInst(0), numOp(0), numLoad(0), lastIcacheStall(0), lastDcacheStall(0)
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{ }
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/** Reads an integer register. */
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RegVal
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readIntRegOperand(const StaticInst *si, int idx) override
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{
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numIntRegReads++;
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const RegId& reg = si->srcRegIdx(idx);
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assert(reg.isIntReg());
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return thread->readIntReg(reg.index());
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}
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/** Sets an integer register to a value. */
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void
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setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
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{
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numIntRegWrites++;
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const RegId& reg = si->destRegIdx(idx);
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assert(reg.isIntReg());
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thread->setIntReg(reg.index(), val);
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}
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/** Reads a floating point register in its binary format, instead
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* of by value. */
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RegVal
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readFloatRegOperandBits(const StaticInst *si, int idx) override
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{
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numFpRegReads++;
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const RegId& reg = si->srcRegIdx(idx);
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assert(reg.isFloatReg());
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return thread->readFloatReg(reg.index());
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}
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/** Sets the bits of a floating point register of single width
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* to a binary value. */
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void
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setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
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{
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numFpRegWrites++;
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const RegId& reg = si->destRegIdx(idx);
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assert(reg.isFloatReg());
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thread->setFloatReg(reg.index(), val);
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}
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/** Reads a vector register. */
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const VecRegContainer &
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readVecRegOperand(const StaticInst *si, int idx) const override
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{
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numVecRegReads++;
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const RegId& reg = si->srcRegIdx(idx);
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assert(reg.isVecReg());
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return thread->readVecReg(reg);
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}
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/** Reads a vector register for modification. */
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VecRegContainer &
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getWritableVecRegOperand(const StaticInst *si, int idx) override
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{
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numVecRegWrites++;
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const RegId& reg = si->destRegIdx(idx);
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assert(reg.isVecReg());
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return thread->getWritableVecReg(reg);
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}
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/** Sets a vector register to a value. */
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void
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setVecRegOperand(const StaticInst *si, int idx,
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const VecRegContainer& val) override
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{
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numVecRegWrites++;
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const RegId& reg = si->destRegIdx(idx);
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assert(reg.isVecReg());
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thread->setVecReg(reg, val);
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}
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/** Vector Register Lane Interfaces. */
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/** @{ */
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/** Reads source vector lane. */
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template <typename VecElem>
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VecLaneT<VecElem, true>
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readVecLaneOperand(const StaticInst *si, int idx) const
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{
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numVecRegReads++;
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const RegId& reg = si->srcRegIdx(idx);
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assert(reg.isVecReg());
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return thread->readVecLane<VecElem>(reg);
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}
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/** Reads source vector 8bit operand. */
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virtual ConstVecLane8
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readVec8BitLaneOperand(const StaticInst *si, int idx) const
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override
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{ return readVecLaneOperand<uint8_t>(si, idx); }
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/** Reads source vector 16bit operand. */
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virtual ConstVecLane16
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readVec16BitLaneOperand(const StaticInst *si, int idx) const
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override
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{ return readVecLaneOperand<uint16_t>(si, idx); }
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/** Reads source vector 32bit operand. */
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virtual ConstVecLane32
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readVec32BitLaneOperand(const StaticInst *si, int idx) const
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override
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{ return readVecLaneOperand<uint32_t>(si, idx); }
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/** Reads source vector 64bit operand. */
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virtual ConstVecLane64
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readVec64BitLaneOperand(const StaticInst *si, int idx) const
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override
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{ return readVecLaneOperand<uint64_t>(si, idx); }
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/** Write a lane of the destination vector operand. */
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template <typename LD>
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void
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setVecLaneOperandT(const StaticInst *si, int idx,
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const LD& val)
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{
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numVecRegWrites++;
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const RegId& reg = si->destRegIdx(idx);
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assert(reg.isVecReg());
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return thread->setVecLane(reg, val);
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}
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/** Write a lane of the destination vector operand. */
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virtual void
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setVecLaneOperand(const StaticInst *si, int idx,
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const LaneData<LaneSize::Byte>& val) override
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{ return setVecLaneOperandT(si, idx, val); }
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/** Write a lane of the destination vector operand. */
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virtual void
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setVecLaneOperand(const StaticInst *si, int idx,
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const LaneData<LaneSize::TwoByte>& val) override
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{ return setVecLaneOperandT(si, idx, val); }
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/** Write a lane of the destination vector operand. */
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virtual void
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setVecLaneOperand(const StaticInst *si, int idx,
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const LaneData<LaneSize::FourByte>& val) override
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{ return setVecLaneOperandT(si, idx, val); }
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/** Write a lane of the destination vector operand. */
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virtual void
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setVecLaneOperand(const StaticInst *si, int idx,
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const LaneData<LaneSize::EightByte>& val) override
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{ return setVecLaneOperandT(si, idx, val); }
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/** @} */
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/** Reads an element of a vector register. */
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VecElem
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readVecElemOperand(const StaticInst *si, int idx) const override
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{
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numVecRegReads++;
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const RegId& reg = si->srcRegIdx(idx);
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assert(reg.isVecElem());
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return thread->readVecElem(reg);
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}
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/** Sets an element of a vector register to a value. */
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void
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setVecElemOperand(const StaticInst *si, int idx,
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const VecElem val) override
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{
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numVecRegWrites++;
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const RegId& reg = si->destRegIdx(idx);
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assert(reg.isVecElem());
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thread->setVecElem(reg, val);
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}
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const VecPredRegContainer&
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readVecPredRegOperand(const StaticInst *si, int idx) const override
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{
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numVecPredRegReads++;
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const RegId& reg = si->srcRegIdx(idx);
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assert(reg.isVecPredReg());
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return thread->readVecPredReg(reg);
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}
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VecPredRegContainer&
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getWritableVecPredRegOperand(const StaticInst *si, int idx) override
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{
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numVecPredRegWrites++;
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const RegId& reg = si->destRegIdx(idx);
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assert(reg.isVecPredReg());
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return thread->getWritableVecPredReg(reg);
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}
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void
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setVecPredRegOperand(const StaticInst *si, int idx,
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const VecPredRegContainer& val) override
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{
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numVecPredRegWrites++;
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const RegId& reg = si->destRegIdx(idx);
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assert(reg.isVecPredReg());
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thread->setVecPredReg(reg, val);
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}
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RegVal
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readCCRegOperand(const StaticInst *si, int idx) override
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{
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numCCRegReads++;
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const RegId& reg = si->srcRegIdx(idx);
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assert(reg.isCCReg());
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return thread->readCCReg(reg.index());
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}
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void
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setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
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{
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numCCRegWrites++;
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const RegId& reg = si->destRegIdx(idx);
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assert(reg.isCCReg());
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thread->setCCReg(reg.index(), val);
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}
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RegVal
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readMiscRegOperand(const StaticInst *si, int idx) override
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{
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numIntRegReads++;
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const RegId& reg = si->srcRegIdx(idx);
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assert(reg.isMiscReg());
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return thread->readMiscReg(reg.index());
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}
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void
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setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
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{
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numIntRegWrites++;
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const RegId& reg = si->destRegIdx(idx);
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assert(reg.isMiscReg());
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thread->setMiscReg(reg.index(), val);
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}
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/**
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* Reads a miscellaneous register, handling any architectural
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* side effects due to reading that register.
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*/
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RegVal
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readMiscReg(int misc_reg) override
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{
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numIntRegReads++;
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return thread->readMiscReg(misc_reg);
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}
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/**
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* Sets a miscellaneous register, handling any architectural
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* side effects due to writing that register.
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*/
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void
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setMiscReg(int misc_reg, RegVal val) override
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{
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numIntRegWrites++;
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thread->setMiscReg(misc_reg, val);
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}
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PCState
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pcState() const override
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{
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return thread->pcState();
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}
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void
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pcState(const PCState &val) override
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{
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thread->pcState(val);
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}
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Fault
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readMem(Addr addr, uint8_t *data, unsigned int size,
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Request::Flags flags,
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const std::vector<bool>& byte_enable = std::vector<bool>())
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override
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{
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assert(byte_enable.empty() || byte_enable.size() == size);
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return cpu->readMem(addr, data, size, flags, byte_enable);
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}
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Fault
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initiateMemRead(Addr addr, unsigned int size,
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Request::Flags flags,
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const std::vector<bool>& byte_enable = std::vector<bool>())
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override
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{
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assert(byte_enable.empty() || byte_enable.size() == size);
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return cpu->initiateMemRead(addr, size, flags, byte_enable);
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}
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Fault
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writeMem(uint8_t *data, unsigned int size, Addr addr,
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Request::Flags flags, uint64_t *res,
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const std::vector<bool>& byte_enable = std::vector<bool>())
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override
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{
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assert(byte_enable.empty() || byte_enable.size() == size);
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return cpu->writeMem(data, size, addr, flags, res, byte_enable);
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}
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Fault amoMem(Addr addr, uint8_t *data, unsigned int size,
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Request::Flags flags, AtomicOpFunctorPtr amo_op) override
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{
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return cpu->amoMem(addr, data, size, flags, std::move(amo_op));
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}
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Fault initiateMemAMO(Addr addr, unsigned int size,
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Request::Flags flags,
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AtomicOpFunctorPtr amo_op) override
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{
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return cpu->initiateMemAMO(addr, size, flags, std::move(amo_op));
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}
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Fault initiateHtmCmd(Request::Flags flags) override
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{
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return cpu->initiateHtmCmd(flags);
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}
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/**
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* Sets the number of consecutive store conditional failures.
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*/
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void
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setStCondFailures(unsigned int sc_failures) override
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{
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thread->setStCondFailures(sc_failures);
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}
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/**
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* Returns the number of consecutive store conditional failures.
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*/
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unsigned int
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readStCondFailures() const override
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{
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return thread->readStCondFailures();
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}
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/** Returns a pointer to the ThreadContext. */
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ThreadContext *tcBase() const override { return thread->getTC(); }
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bool
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readPredicate() const override
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{
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return thread->readPredicate();
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}
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void
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setPredicate(bool val) override
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{
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thread->setPredicate(val);
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if (cpu->traceData) {
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cpu->traceData->setPredicate(val);
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}
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}
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bool
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readMemAccPredicate() const override
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{
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return thread->readMemAccPredicate();
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}
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void
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setMemAccPredicate(bool val) override
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{
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thread->setMemAccPredicate(val);
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}
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uint64_t
|
|
getHtmTransactionUid() const override
|
|
{
|
|
return tcBase()->getHtmCheckpointPtr()->getHtmUid();
|
|
}
|
|
|
|
uint64_t
|
|
newHtmTransactionUid() const override
|
|
{
|
|
return tcBase()->getHtmCheckpointPtr()->newHtmUid();
|
|
}
|
|
|
|
bool
|
|
inHtmTransactionalState() const override
|
|
{
|
|
return (getHtmTransactionalDepth() > 0);
|
|
}
|
|
|
|
uint64_t
|
|
getHtmTransactionalDepth() const override
|
|
{
|
|
assert(thread->htmTransactionStarts >= thread->htmTransactionStops);
|
|
return (thread->htmTransactionStarts - thread->htmTransactionStops);
|
|
}
|
|
|
|
/**
|
|
* Invalidate a page in the DTLB <i>and</i> ITLB.
|
|
*/
|
|
void
|
|
demapPage(Addr vaddr, uint64_t asn) override
|
|
{
|
|
thread->demapPage(vaddr, asn);
|
|
}
|
|
|
|
void
|
|
armMonitor(Addr address) override
|
|
{
|
|
cpu->armMonitor(thread->threadId(), address);
|
|
}
|
|
|
|
bool
|
|
mwait(PacketPtr pkt) override
|
|
{
|
|
return cpu->mwait(thread->threadId(), pkt);
|
|
}
|
|
|
|
void
|
|
mwaitAtomic(ThreadContext *tc) override
|
|
{
|
|
cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb);
|
|
}
|
|
|
|
AddressMonitor *
|
|
getAddrMonitor() override
|
|
{
|
|
return cpu->getCpuAddrMonitor(thread->threadId());
|
|
}
|
|
};
|
|
|
|
#endif // __CPU_EXEC_CONTEXT_HH__
|